ICS8431-11 Datasheet, PDF (9/13 Pages) Integrated Circuit Systems – 255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER,
LVPECL FREQUENCY SYNTHESIZER
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation tech-
nique for EMI reduction. When spread-spectrum is enabled, a
30KHz triangle waveform is used with 0.5% down-spread
(+0.0% / -0.5%) from the nominal 200MHz clock frequency.
An example of a triangle frequency modulation profile is shown
in Figure 2 below. The ramp profile can be expressed as:
• Fnom = Nominal Clock Frequency in Spread OFF mode
(200MHz with 16MHz IN)
• Fm = Nominal Modulation Frequency (30KHz)
• δ = Modulation Factor (0.5% down spread)
(1
-
δ)
fnom
+
2
fm
x
δ
x
fnom
x
t
when
0
<
t
<
1
2 fm
,
(1
-
δ)
fnom
-
2
fm
x
δ
x
fnom
x
t
when
1
2 fm
<
t
<
1
fm
The ICS8431-11 triangle modulation frequency deviation will
not exceed 0.6% down-spread from the nominal clock fre-
quency (+0.0% / -0.5%). An example of the amount of down
spread relative to the nominal clock frequency can be seen in
the frequency domain, as shown in Figure 3. The ratio of this
width to the fundamental frequency is typically 0.4%, and will
not exceed 0.6%. The resulting spectral reduction will be
greater than 7dB, as shown in Figure 3. It is important to note
the ICS8431-11 7dB minimum spectral reduction is the com-
ponent-specific EMI reduction, and will not necessarily be the
same as the system EMI reduction.
Fnom
(1 - δ) Fnom
0.5/fm
➤
1/fm
FIGURE 2. TRIANGLE FREQUENCY MODULATION
∆ − 10 dBm
B
A
δ = .4%
FIGURE 3. 200MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN
(A) SPREAD-SPECTRUM OFF
(B) SPREAD-SPECTRUM ON
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8431-11 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VDD, VDDI, VDDA, and
VDDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be used
for each pin. To achieve optimum jitter performance, better
power supply isolation is required. Figure 4 illustrates how a
10Ω along with a 10µF and a .01µF bypass capacitor should
be connected to each power supply pin.
VDD
3.3V
.01µF 10Ω
VDDA
.01µF
10 µF
FIGURE 4. POWER SUPPLY FILTERING
ICS8431CM-11
www.icst.com/products/hiperclocks.html
9
REV. A JULY 11, 2001