ICS8431-11 Datasheet, PDF (7/13 Pages) Integrated Circuit Systems – 255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER,
LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
The ICS8431-11 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth.
A 16MHz series-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by
16 prior to the phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates over
a range of 190 to 510MHz. The output of the loop divider is also applied to the phase detector.
The phase detector and the loop filter force the VCO output frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to the LVPECL output buffer. The divider provides a 50% output duty cycle.
The programmable features of the ICS8431-11 support four output operational modes and a programmable PLL loop divider.
The four output operational modes are spread spectrum clocking (SSC), non-spread spectrum clock and two test modes and
are controlled by the SSC_CTL[1:0] pins.
The PLL loop divider or M divider is programmed by using inputs M0 through M8. While the nP_LOAD input is held LOW, the
data present at M0:M8 is transparent to the M-divider. On the LOW-to-HIGH transition of nP_LOAD, the M0:M8 data is latched
into the M-divider and any further changes at the M0:M8 inputs will not be seen by the M-divider until the next LOW transition
on nP_LOAD.
The relationship between the VCO frequency, the crystal frequency and the loop counter/divider is defined as follows:
fVCO
=
fxtal
16
x
M
The M count and the required values of M0:M8 for programming the VCO are shown in Table 3B, Programmable VCO Frequency
Function Table. The frequency out is defined as follows:
FOUT
=
fVCO
2
=
fxtal x
32
M
For the ICS8431-11, the output divider equals 2. Valid M values for which the PLL will achieve lock are defined as 190 ≤ M ≤ 510.
ICS8431CM-11
www.icst.com/products/hiperclocks.html
7
REV. A JULY 11, 2001