ICS8431-11 Datasheet, PDF (11/13 Pages) Integrated Circuit Systems – 255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER,
LVPECL FREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C1, C2 and C3, C4, C5, C6 as
close as possible to the power pins. If space allows, placing the
decoupling capacitor at the component side is preferred. This can
reduce unwanted inductance between the decoupling capacitor
and the power pin generated by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
If VDDA shares the same power supply with VDD, insert the RC
filter R5, C3, and C4 in between. Place this RC filter as close to
the VDDA as possible.
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should
be arranged to achieve the best clock signal quality. Poor clock
signal quality can degrade the system performance or cause
system failure. In the synchronous high-speed digital system,
the clock signal is less tolerable to poor signal quality than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The trace shape and the trace
delay might be restricted by the available space on the board and
the component location. While routing the traces, the clock signal
traces should be routed first and should be locked prior to routing
other signals traces.
• The traces with 50Ω transmission lines TL1 and TL2 at
FOUT and nFOUT should have equal delay and run ad-
jacent to each other. Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
• Keep the clock trace on same layer. Whenever possible,
avoid any vias on the clock traces. Any via on the trace
can affect the trace characteristic impedance and hence
degrade signal quality.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
• Make sure no other signal trace is routed between the
clock trace pair.
The matching termination resistors R1, R2, R3 and R4 should be
located as close to the receiver input pins as possible. Other termi-
nation scheme can also be used but is not shown in this example.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
26 (XTAL1) and 25 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
ICS8431CM-11
U1
ICS8431-11
C6
C3
C4
R5
C2
GND
VDD
X1
Signals
VIA
TL1 (50 Ohm)
Close to the input
pins of the
receiver
R1
R2
IN+
C1
TL2 (50 Ohm)
IN-
R3
R4
FIGURE 6B. PCB BOARD LAYOUT FOR ICS8431-11
www.icst.com/products/hiperclocks.html
11
REV. A JULY 11, 2001