ICS8431-11 Datasheet, PDF (10/13 Pages) Integrated Circuit Systems – 255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER,
LVPECL FREQUENCY SYNTHESIZER
TERMINATION FOR PECL OUTPUTS
The clock layout topology shown below is typical for
IA64/32 platforms. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/PECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion. There are a few simple termination
schemes. Figures 5A and 5B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
Z_o = 50Ω
Z_o = 50Ω
FOUT
FIN
Z_o = 50Ω
50Ω
1
RTT =
Z_o
(VOH + VOL / VCC –2) –2
Z_o = 50Ω
50Ω
VCC-2V
RTT
FOUT
5
2 ^Zo
Z_o = 50Ω
3.3V
5
2 ^Zo
Z_o = 50Ω
FIN
Z
o
=
50Ω
3
2 ^Zo
Z
o
=
50Ω
3
2 ^Zo
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
LAYOUT GUIDELINE
The schematic of the ICS8431-11 layout example used in this layout guideline is shown in Figure 6A. The ICS8431-11 recommended
PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual
system will depend on the selected component types, the density of the components, the density of the traces, and the stacking of
the P.C. board.
VDD
U1
1
2
3
4
M0
M1
M2
5
6
7
8
M3
M4
M5
M6
9
10
M7
M8
11
12
SSC_CTL0
SSC_CTL1
13
14
GND
TEST_IO
VDD
28
nP_LOAD
VDDI
XTAL1
27
26
25
XTAL2
NC
NC
VDDA
24
23
22
21
NC
NC
20
19
NC
VDDO
18
17
FOUT
nFOUT
16
15
GND
C1
0.1uF
8431-11
VDD
C6
0.01uF
VDD
X1
VDDA
C3
0.01uF
R5
10
C4
10uF
Zo = 50 Ohm
C2
0.1uF
TL1
Zo = 50 Ohm
TL2
Termination A
VDD0
R1
125
IN+
R3
125
IN-
R2
R4
84
84
Termination
B (not shown
in the layout)
IN+
IN-
R2
R1
50
50
R3
50
ICS8431CM-11
FIGURE 6A. RECOMMENDED SCHEMATIC LAYOUT
www.icst.com/products/hiperclocks.html
10
REV. A JULY 11, 2001