ICS2002 Datasheet, PDF(9/21 Page) Integrated Circuit Systems

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ICS2002 Datasheet, PDF (9/21 Pages) Integrated Circuit Systems – Wavedec Digital Audio Codec

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ICS2002

Direct Register Descriptions

The base address is determined externally by an address de-

coder which selects the chip via the CS input.

Status (Base + 0 read)

Note that this register can only be read in STAND ALONE

mode. Hence, indirect access to this register has been provided

at RA=83h for use in COMPANION mode.

765 432 1 0

Clear Play IRQ

Clear Record IRQ

reserved

Power-Down Mode IRQ

FIFO Overflow/Underflow IRQ

Sample Rate IRQ

FIFO Ready

IRQ (same as pin)

This register is the indirect pointer to direct data transfers to

and from the data registers. It is a read/write register. Note that

this register can only be read if the chip is in STAND ALONE

mode.

Data Low Byte/Word (DLW)

765 432 1 0

IRQ Reset (Base + 0 write)

765 432 1 0

Clear PLAY IRQ

Clear REC IRQ

reserved

Clear PDM IRQ

Clear FOU IRQ

Clear SR IRQ

reserved

Data High Byte (DH) (Base + 3)

765 432 1 0

These two addresses are used to accomplish all internal register

reading and writing. Most internal registers are 8-bit or less.

These are accessed by first writing the appropriate value to the

DW, then writing (reading) the data byte to (from) DLW.

This register provides the driver software easy access to the

interrupt source when read. Note that bit 7 indicates the state

of the IRQ pin, and hence will be zero when the MIE bit is zero

(see âInterrupt Enableâ register).

A write to the register is performed to clear interrupts. Writing

a one to a given bit will cause the associated interrupt to be

cleared. To release the clear interrupt bit and allow further

interrupts to occur, a zero must be written back to the bit of

interest (some bits have alternate methods of clearing described

later). This feature ensures that if the interrupt condition still

exists, an edge will be generated on the IRQ pin, thus ensuring

recognition on platforms that are edge sensitive. This also

allows for a return from interrupt instruction to be executed on

the platform while the IRQ line is inactive.

I/O Mode FIFO data (RA=0Bh), Algorithm RAM, and Coeffi-

cient RAM are always treated as 16-bit entities, and can be

transferred in two ways:

- a single operation to/from DLW with SBHE = 0

- two successive operations, low byte to/from DLW

with SBHE = 1, then high byte to/from DH.

Bit 6 is a special case. There is no IRQ associated with this bit.

It is located here for use in Sound Source Emulation Mode, and

represents the BUSY status of a Sound Source. When the

STATUS is read and tested with 40h, a zero result indicates that

the play FIFO is full.

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