ICS2002 Datasheet, PDF (17/21 Pages) Integrated Circuit Systems – Wavedec Digital Audio Codec

ICS2002
IR99 Record DMA Burst Count (RDMABC)
Bits 7:6 - reserved
Bits 5:0 - Record DMA Burst Count
This value determines the number of DMA transfers
that take place for each DMA request issued to the host.
The actual number of transfers will be RDMABC + 1.
Thus, for single transfer mode, program this register to
zero. The burst counter is automatically preset to the
burst count whenever the DACKR input is high. Thus,
there is no need to reprogram the count value after TC,
since the next transfer will use the full programmed
count value. This register has no affect on I/O Mode
data transfers, since its only influence is over the DRQR
output. This register is not initialized by any means
other than a direct write, and hence must be written to
before DMA is enabled.
IR9A Record DMA Mode (RDMAMODE)
All bits in this register are cleared by MCR.
Bit 2 - 16-Bit DMA (RDMA16)
When set to a one, this bit causes the hardware to expect
data to be sent in 16-bit words. When low, the hardware
expects 8-bit bytes. This bit must be set to one when
performing I/O mode transfers, as all I/O transfers are
treated as 16-bit entities.
Bits 1:0 - Record Data Type (RDATATYPE)
These bits direct the hardware how to interpret the
incoming data. Note that this is independent of the
DMA or I/O data width. It effects how data is “signed”
and how data is packed to/unpacked from the Record
FIFO.
Value
00
01
10
11
Data Type
8-bit linear
16-bit linear
reserved
reserved
Bits 7:6 - reserved
Bit 5 - Terminal Count Interrupt (RTCIRQ) (read only)
This bit indicates that a Terminal Count has been re-
ceived on the last DMA operation. If the RECIE bit has
been programmed to a one, an interrupt will be gener-
ated at the end of the last DMA operation. This bit is
cleared by MCR or a write to STATUS with bit 1 = 1.
The reset state is then removed by either writing the
STATUS bit 0 to 0, or by the next DMA operation.
Hence, there is no need to “remove” this reset as there
is for other IRQ reset operations.
Bit 4 - Record I/O Mode Transfer (RIOXFER)
When this bit is a one, the DMA hardware (DRQR and
RTCIRQ) is disabled. Data transfers take place via RA
$8B (NOT $9B), and are required to be treated as 16-bit
transfers. Thus, data should be read from DLW (with
SBHE = 0, 16-bit data) or from DLW (with SBHE = 1,
8-bit data low byte) followed by DH (8-bit data, high
byte). It is also the programmers responsibility to en-
sure that RDMAMODE bit 1 (RDMA16) is set to a one
for all I/O mode transfers.
Bit 3 - Unsigned Data (RUSIGN)
When set to a one, the record FIFO will generate
unsigned data. The native data format is Signed Binary
Twos Complement. This bit will invert the most signifi-
cant bit of each data byte (or word, depending on the
state of RDATATYPE).
IR9B reserved
Record FIFO Control/Status Registers
IR9C Record FIFO Enable/Status (RFES)
Bit 0 - Record FIFO Enable (RFE)
This bit holds the record FIFO in a reset state when low,
and enables the FIFO to operate when high. This bit is
reset by MCR. This bit, when low, also resets all FIFO
related conditions (see the following bits) and prevents
DMA start requests from being issued. It does not reset
the Record FIFO IRQ Mode register.
Bit 1 - FIFO Overflow (read only)
This bit is set when a FIFO shift in command is gener-
ated (by either DMA, I/O, or the DSP) with the FIFO
full, and indicates an error condition. This bit will cause
the FOUIRQ bit to go active, generating an IRQ if
enabled. This bit is reset by writing to STATUS with bit
4 = 1, and re-enabled by writing to STATUS with bit 4
= 0. FE low also resets this bit.
Bit 2 - FIFO Underflow (read only)
This bit is set when a FIFO shift out command is
generated (by either DMA, I/O, or the DSP) with the
FIFO empty, and indicates an error condition. This bit
will cause the FOUIRQ bit to go active, generating an
IRQ if enabled. This bit is reset by writing to STATUS
with bit 4 = 1, and re-enabled by writing to STATUS
with bit 4 = 0. FE low also resets this bit.
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