ICS2002 Datasheet, PDF (13/21 Pages) Integrated Circuit Systems – Wavedec Digital Audio Codec

ICS2002
Play DMA Control and Status Registers
IR88 Play DMA Control (DMACTL)
Bits 7 - reserved
Bit 6 - TC Reset Mask
When set to 1, this bit masks the ‘DMA Run’ bit reset
upon receipt of TC, terminal count, signal from the ISA
bus. When reset to 0, the ‘DMA Run’ bit will be reset
upon receipt of TC.
Bits 5:1 - reserved
Bit 0 - DMA Run
This bit enables the DMA hardware to begin transfer-
ring data when set to one. It is cleared by either MCR
or receipt of a TC when ‘TC Reset Mask’ is a zero (see
the DMAMODE register for details).
IR89 Play DMA Burst Count (DMABC)
Bits 7:6 - reserved
Bits 5:0 - DMA Burst Count
This value determines the number of DMA transfers
that take place for each DMA request issued to the host.
The actual number of transfers will be DMABC+1.
Thus, for single transfer mode, program this register to
zero. The burst counter is automatically preset to the
burst count whenever the DACKP input is high. Thus,
there is no need to reprogram the count value after TC,
since the next transfer will use the full programmed
count value. This register has no affect on I/O Mode
data transfers, since its only influence is over the DRQP
output. This register is not initialized by any means
other than a direct write, and hence must be written to
before DMA is enabled.
IR8A Play DMA Mode (DMAMODE)
All bits in this register are cleared by MCR.
Bits 7:6 - reserved
Bit 5 - Terminal Count Interrupt (TCIRQ) - (read only)
This bit indicates that a Terminal Count has been re-
ceived on the last DMA operation. If the PFIE and
PLAYIRQ bits have been programmed to a one, an
interrupt will be generated at the end of the last DMA
operation. This bit is cleared by MCR or a write to
STATUS with bit 0 = one. The reset state is then
removed by either writing the STATUS bit 0 to zero.
Bit 4 - I/O Mode Transfer (IOXFER)
When this bit is a one, the DMA hardware (DRQP and
TCIRQ) is disabled. Data transfers take place via IR8Bh,
and are required to be treated as 16-bit transfers. Thus, data
should be written to DLW (withSBHE = low, 16-bit data)
or to DLW (with SBHE = high, 8-bit data low byte)
followed by DH (8-bit data, high byte). It is also the
programmers responsibility to ensure that DMAMODE
bit 2 (DMA16) is set to a one for all I/O mode transfers.
Bit 3 - Unsigned Data (USIGN)
When set to a one, this bit expects to receive (and will
generate) unsigned data. The native data format is
Signed Binary Twos Complement. This bit will invert
the most significant bit of each data byte (or word,
depending on the state of DATATYPE). Note that this
bit should be zero when the DATATYPE indicates
u-law or A- law data formats.
Bit 2 - 16 Bit Data (DMA16)
When set to a one, this bit causes the hardware to expect
data to be sent in 16-bit words. When low, the hardware
expects 8-bit bytes. This bit must be set to one when
performing I/O mode transfers, as all I/O transfers are
treated as 16 bit values.
Bit 1:0 - Data Type (DATATYPE)
These bits direct the hardware how to interpret the
outgoing data. This is independent of the DMA or I/O
data width. It effects how data is signed and how data
is packed to and unpacked from the Play FIFO. The
DATATYPE field selects the format of data for playback.
Value
00
01
10
11
Data Type
8-bit linear
16-bit linear
8-bit µ256 Law
8-bit A-Law
IR8B DMA I/O Mode Data Port (DMADATA) (8/16-bit)
This register address is used to trap I/O mode data to
and from the FIFOs. It is only used in I/O mode. See
the description of the IOXFER bits for more details.
When DMA16 is one, this register MUST be accessed
as a sixteen bit value. Note that this can be done from
either an eight or sixteen bit ISA slot, since the chip used
SBHE to determine the proper byte swapping.
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