ICS2002 Datasheet, PDF (15/21 Pages) Integrated Circuit Systems – Wavedec Digital Audio Codec

ICS2002
IR8E reserved
IR8F Play FIFO Output Data Read Back (8/16 bit)
This register is provided for test use only, although it may find
system level use as a diagnostic tool.
Power Control and Status
IR90 Power Enable/Status (PEST)
Bit 7 - PWRIRQ (read only)
This bit is a one when either edge has occurred on the
PWRDN pin, and the edge enable in the Power Mode
register is set. If bit 3 of the MIE is one, this will also
generate an external interrupt. In any case, this bit is
also visible as STATUS register bit 3. PWRIRQ is reset
by disabling both edge enable bits or resetting the edge
interrupts (see below).
Bits 6:5 - reserved
Bit 4 - ADCPWR Disable
This bit controls the power state of the ADC analog
circuitry. When 0, ADC analog power is controlled by
the SOFTPWR bit the same as the DAC analog power
is. When this bit is set to a 1, the ADC analog power is
turned off independent of the state of SOFTPWR.
This feature is included for advanced power manage-
ment routines, as chip power dissipation can be reduced
by almost half by turning ADC power off when not in
use. Note, however, that several milliseconds of settling
time is required after power is turned on before the ADC
functions properly.
Bit 3 - PWRDN Pin Value (read only)
This bit indicates the state of the PWRDN pin.
Bit 2 - FALLIRQ (read only)
This bit is set when the PWRDN pin makes a transition
from high to low. If PWRMODE bit 2 (FALLIE) is one,
this will cause PWRIRQ to go high as well. This bit is
reset by one of the following:
- MCR
- any write to PEST
- a write to STATUS with bit 3 set to one. This will hold
the bit reset until released by a write to STATUS with
bit 3 cleared to zero.
Note that FALLIE does not mask this bit, allowing
polling to be performed.
Bit 1 - RISEIRQ (read only)
This bit is set when the PWRDN pin makes a transition
from low to high. If PWRMODE bit 1 (RISEIE) is one,
this will cause PWRIRQ to go high as well. This bit is
reset by one of the following:
- MCR
- any write to PEST
- a write to STATUS with bit 3 set to one. This will
hold the bit reset until released by a write to STATUS
with bit 3 cleared to zero.
Note that RISEIE does not mask this bit, allowing
polling to be performed.
Bit 0 - Soft Power (SOFTPWR)
The function of this bit depends on the status of the
“SWMODE” bit (bit 0 of PWRMODE). When
SWMODE is zero, writes to this bit have no affect.
Reads will return the state of the PWRDN* pin, which
is also the state of the on chip PWRON control signal.
When SWMODE is a one, a write of one to this bit turns
on power to the chip analog circuitry, while a zero clears
this bit and puts the chip in a low power mode. Reads
will return the last value written.
IR91 Power Mode (PWRMODE)
All bits in this register are cleared by MCR.
Bits 7:3 - reserved
Bit 2 - Fall IRQ Enable (FALLIE)
When set to one, this bit allows a falling edge on
PWRDN to cause PWRIRQ to go high. It does not mask
PEST bit 2.
Bit 1 - Rise IRQ Enable (RISEIE)
When set to one, this bit allows a rising edge on
PWRDN to cause PWRIRQ to go high. It does not mask
PEST bit 1.
Bit 0 - Software Mode (SWMODE)
When cleared to zero, this bit causes the chip to operate
in a “hardware driven” mode; that is, the PWRDN pin
directly controls the chip analog power (for low power
consumption). In this mode, a low on PWRDN puts the
chip in low power mode, while a high enables normal
operation. When set to a one, this bit causes the chip to
operate in a “software driven” mode. In this mode,
changes on the PWRDN pin only generate interrupts.
The hardware low power mode is then controlled (via
software) by SOFTPWR (bit 0 of PEST). This function
allows “clean” software controlled turn on and off of
the analog circuitry power.
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