ICS2002 Datasheet, PDF (8/21 Pages) Integrated Circuit Systems – Wavedec Digital Audio Codec

ICS2002
Digital Audio Playback
To play digital audio files, the chip is programmed for the
desired sample rate, data type, DMA channel width, and output
volume.
For DMA mode playback, DRQ generation is programmable
for servicing the FIFO at several levels. This allows optimal
performance with a variety of hosts. When TC is received, the
chip will optionally generate an interrupt to the host to indicate
the need to service the DMA controller.
For I/O Mode playback, data is written to the FIFO until it is
full. This is determined by polling the “DIR” bit of the status
register. Once the FIFO is full, an interrupt will be generated
optionally at one of several selectable points: 1/4, 1/2, or 3/4
full. The host can then burst a predetermined amount of data to
the FIFO and wait for the next interrupt.
Digital Audio Recording:
Audio recording operates in a DMA or I/O mode similarly to
audio playback with the audio input programmable as a line or
microphone level input. Simultaneous record and playback is
supported and permits the recorded file to be synchronized to
an existing file. The new and existing file can then be mixed
digitally for high quality results.
Power Management:
The PWRDN input can be programmed to act as an immediate
hardware power control, or as an interrupt source for a software
driven power management routine. The software driven option
allows the driver to cleanly shut down to chip, thus preventing
unwanted noise. When active, the power-down function dis-
ables all analog components including the oscillator, and causes
the chip to enter a low power mode.
Miscellaneous Functions:
The chip has a full complement of status and control functions.
All significant functions are capable of generating interrupts
and/or being polled.
The DMA can be run in single or demand mode (for bursts of
data in programmed sizes).
The FIFO has programmable interrupt and DMA request ca-
pacities, and also indicates when overflow or underflow condi-
tions occur.
The processor interface is designed for simple connection to
the ISA bus. For best noise performance, isolating the data lines
from the ISA bus is recommended. In general, feed through of
digital noise is reduced by minimizing the load which the
digital outputs are driving.
Data Processing:
To simplify the external circuitry associated with the analog
input and output signals of the chip, input and output sample
rates are oversampled. This allows simple RC filters to be used.
For playback, the output data is oversampled, interpolated,
filtered and scaled. Since the DSP is fully programmable,
various sample rates and filter shapes can be implemented. The
processed data is then output to the DAC. The DAC output
passes through an analog volume control (4 bits, 1.5dB steps)
before being passed to the analog filter stage.
For recording, the input data is first filtered, removing most of
the frequency content above the Nyquist frequency. The result-
ing data stream is then undersampled to the desired sample rate
and fed into the FIFO for transfer to the host.
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