DT72281_13 Datasheet, PDF (9/26 Pages) Integrated Device Technology – CMOS SuperSync FIFO

IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
87
87
87
87
IDT72281 (65,536 x 9 ⎯ BIT)
0
EMPTY OFFSET (LSB) REGISTER
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
IDT72291 (131,072 x 9 ⎯ BIT)
87
0
EMPTY OFFSET (LSB) REGISTER
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
0
EMPTY OFFSET (MSB) REGISTER
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
87
0
EMPTY OFFSET (MID-BYTE) REGISTER
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
0
FULL OFFSET (LSB) REGISTER
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
0
FULL OFFSET (MSB) REGISTER
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
8
87
87
10
EMPTY OFFSET
(MSB) REGISTER
DEFAULT
0H
0
FULL OFFSET (LSB) REGISTER
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
0
FULL OFFSET (MID-BYTE) REGISTER
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
8
Figure 3. Offset Register Location and Default Values
10
FULL OFFSET
(MSB) REGISTER
DEFAULT
0H
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LD WEN REN SEN WCLK
001 1
010 1
X
011 0
X1 1 1
X
1 0X X
RCLK
IDT72281
IDT72291
X
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
X
Serial shift into registers:
32 bits for the IDT72281
Serial shift into registers:
34 bits for the IDT72291
1 bit for each rising WCLK edge 1 bit for each rising WCLK edge
Starting with Empty Offset (LSB) Starting with Empty Offset (LSB)
Ending with Full Offset (MSB) Ending with Full Offset (MSB)
X
No Operation
No Operation
X
Write Memory
Write Memory
1X 0 X
X
Read Memory
Read Memory
111 X
X
X
No Operation
No Operation
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 4. Programmable Flag Offset Programming Sequence
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9