DT72281_13 Datasheet, PDF (22/26 Pages) Integrated Device Technology – CMOS SuperSync FIFO

IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
tCLK
tCLKH
tCLKL
tLDS
tLDH
tLDH
LD
WEN
D0 - D7
tENS
tDS
PAE OFFSET
(LSB)
tENH
tDH
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
tENH
tDH
PAF OFFSET
(MSB)
4675 drw 17
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72281
WCLK
tCLK
tCLKH
tCLKL
tLDS
tLDH
LD
tLDH
WEN
D0 - D7
tENS
tDS
PAE OFFSET
(LSB)
tENH
tDH
PAE OFFSET
(MID-BYTE)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MID-BYTE)
tENH
tDH
PAF OFFSET
(MSB)
4675 drw 18
Figure 15. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72291
RCLK
LD
REN
Q0 - Q7
NOTE:
1. OE = LOW.
t CLKH
t CLK
t CLKL
t LDS
t ENS
t LDH
t ENH
t LDH
t ENH
tA
DATA IN OUTPUT
REGISTER
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
tA
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
4675 drw 19
Figure 16. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72281
RCLK
LD
REN
t CLK
t CLKH
t CLKL
t LDS
t ENS
t LDH
t ENH
t LDH
t ENH
Q0 - Q7
NOTE:
1. OE = LOW.
tA
DATA IN OUTPUT REGISTER
PAE OFFSET
(LSB)
PAE OFFSET
(MID-BYTE)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
tA
PAF OFFSET
(MID-BYTE)
PAF OFFSET
(MSB)
4675 drw 20
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72291
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