DT72281_13 Datasheet, PDF (23/26 Pages) Integrated Device Technology – CMOS SuperSync FIFO

IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t CLKH
t CLKL
WCLK
WEN
PAF
t ENS
1
t ENH
D - (m+1) words in FIFO⁽²⁾
2
1
2
t PAF
tSKEW2 ⁽³⁾
D - m words in FIFO⁽²⁾
t PAF
D-(m+1) words
in FIFO⁽²⁾
RCLK
t ENS
t ENH
REN
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NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 65,536 for the IDT72281 and 131,072 for the IDT72291.
In FWFT mode: D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAF). If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 18. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t CLKH
WCLK
WEN
t CLKL
t ENS
t ENH
PAE
n words in FIFO ^(2),
n+1 words in FIFO ⁽³⁾
t SKEW2(4)
t PAE
n+1 words in FIFO ^(2),
n+2 words in FIFO ⁽³⁾
n words in FIFO ^(2),
n+1 words in FIFO ⁽³⁾
t PAE
RCLK
1
2
1
2
t ENS
t ENH
REN
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NOTES:
1. n = PAE offset.
2. For IDT Standard mode.
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAE). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
Figure 19. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
HF
tCLKH
tCLKL
tENS
D/2 words in FIFO⁽¹⁾,
[ ] D-1
2 ⁺¹
words in FIFO⁽²⁾
tENH
tHF
D/2 + 1 words in FIFO⁽¹⁾,
[ ] D-1
2 +2
words in FIFO⁽²⁾
tHF
D/2 words in FIFO⁽¹⁾,
[ ] D-1
2 +1
words in FIFO⁽²⁾
RCLK
tENS
REN
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 65,536 for the IDT72281 and 131,072 for the IDT72291.
2. For FWFT mode: D = maximum FIFO depth. D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
Figure 20. Half-Full Flag Timing (IDT Standard and FWFT Modes)
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