DT72281_13 Datasheet, PDF (24/26 Pages) Integrated Device Technology – CMOS SuperSync FIFO

IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the EF and FF functions in IDT Standard mode and the IR
and OR functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary
by one cycle between FIFOs. In IDT Standard mode, such problems can be
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can be
created by ORing OR of every FIFO, and separately ORing IR of every FIFO.
Figure 23 demonstrates a width expansion using two IDT72281/72291
devices. D0 - D8 from each device form a 18-bit wide input bus and Q0-Q8 from
each device form a 18-bit wide output bus. Any word width can be attained by
adding additional IDT72281/72291 devices.
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
DATA IN
m+n
D0 - Dm ^m
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) _#1
FULL FLAG/INPUT READY (FF/IR) #2
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
Dm+1 - Dn
n
IDT
72281
72291
FIFO
#1
m
IDT
72281
72291
FIFO
#2
NOTES:
Q0 - Qm
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
EMPTY FLAG/OUTPUT READY (EF/OR) #2
n _{Qm+1 - Qn}
m+n
DATA OUT
(1)
GATE
4675 drw 24
Figure 21. Block Diagram of 65,536 x 18 and 131,072 x 18 Width Expansion
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