DT72281_13 Datasheet, PDF (21/26 Pages) Integrated Device Technology – CMOS SuperSync FIFO

IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK
tENS
REN
Q0 - Qn
Wx
WCLK
WEN
RT
OR
PAE
HF
PAF
tENH _tRTS
tRTS
tENS
1
tSKEW2
1
Wx+1
2
tENH
tREF
tHF
tPAF
2
3
4
tENH
tENH
tA
W1 ⁽⁴⁾
tA
W2
W3
tPAE
tREF ⁽⁵⁾
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NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D – 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
procedure. D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. OR goes LOW at 60 ns + 2 RCLK cycles + tREF.
Figure 12. Retransmit Timing (FWFT Mode)
WCLK
SEN
LD
SI
tENS
tLDS
tDS
BIT 0
tENH
tLDH
EMPTY OFFSET
NOTE:
1. X = 15 for the IDT72281 and X = 16 for the IDT72291.
(1)
BIT X
BIT 0
FULL OFFSET
tENH
tLDH
tDH
(1)
BIT X
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
21
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