ICS9DB306 Datasheet, PDF (8/16 Pages) Integrated Circuit Systems – PCI Express, Jitter Attenuator

Integrated
Circuit
Systems, Inc.
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
Z_o = 50Ω
FOUT
FIN
Z_o = 50Ω
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
Z_o
50Ω
V_CC - 2V
RTT
FIGURE 3A. LVPECL OUTPUT TERMINATION
FOUT
3.3V
125Ω
125Ω
Z_o = 50Ω
FIN
Z_o = 50Ω
84Ω
84Ω
FIGURE 3B. LVPECL OUTPUT TERMINATION
9DB306BL
www.icst.com/products/hiperclocks.html
8
REV. A APRIL 7, 2005