ICS9DB306 Datasheet, PDF (10/16 Pages) Integrated Circuit Systems – PCI Express, Jitter Attenuator

Integrated
Circuit
Systems, Inc.
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS9DB306 application
schematic. In this example, the device is operated at V = 3.3V.
CC
The decoupling capacitor should be located as close as pos-
sible to the power pin. The input is driven by a HCSL driver. For
LVPECL output drivers, one of terminations approaches is shown
in this schematic. For additional termination approaches, please
refer to the LVPECL Termination Application Note.
VCC
R7 24
VCCA
C16
10uF
C11
0.1uF
VCC
R11
1K
VCC
R12 33
HCSL R13 33
R1
50
Zo = 50
Zo = 50
R2
R10
50
1K
U1
VCC
15
16
VCC
17
18
19
PCIEXC5
PCIEXT5
FS1
20
21
22
23
24
25
BY PASS
VEE
VCCA
PLL_BW
CLK
nCLK
26
27
28
FS0
PCIEXT0
PCIEXC0
VCC
ICS9DB306
VEE
14
13
PCIEXT4
PCIEXC4
PCIEXT3
12
11
10
PCIEXC3
VCC
nOE1
nOE0
VCC
PCIEXC2
9
8
7
6
5
4
PCIEXT2
PCIEXC1
PCIEXT1
3
2
1
VEE
VCC
VCC=3.3V
(U1-15) (U1-28)
VCC
(U1-6)
(U1-9)
C1
0.1uF
C2
0.1uF
C3
0. 1uF
C3
0.1uF
Zo = 50
Zo = 50
+
-
LVPECL
R4 R5
50 50
R6
50
R8
R9
1K
1K
Zo = 50
Zo = 50
+
-
R14 R15
50 50
LVPECL
R16
50
FIGURE 5. EXAMPLE OF ICS9DB306 SCHEMATIC
9DB306BL
www.icst.com/products/hiperclocks.html
10
REV. A APRIL 7, 2005