ICS9DB306 Datasheet, PDF (7/16 Pages) Integrated Circuit Systems – PCI Express, Jitter Attenuator

Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS9DB306 provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL. V_CC and V_CCA should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required. Figure 1 illus-
trates how a 24Ω resistor along with a 10μF and a .01μF by-
pass capacitor should be connected to each V_CCA pin.
V_CC
V_CCA
3.3V
.01μF 24Ω
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V_CC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V_CC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLKx
nCLKx
R2
1K
9DB306BL
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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7
REV. A APRIL 7, 2005