ICS9DB306 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – PCI Express, Jitter Attenuator

Integrated
Circuit
Systems, Inc.
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 14, 20
2, 3
4, 5
6, 9, 15, 28
7, 8
10, 11
12, 13
16, 17
18
19
21
22
V_EE
PCIEXT1,
PCIEXC1
PCIEXT2,
PCIEXC2
V_CC
nOE0, nOE1
PCIEXC3,
PCIEXT3
PCIEXC4,
PCIEXT4
PCIEXC5,
PCIEXT5
FS1
BYPASS
V_CCA
PLL_BW
Power
Output
Output
Power
Input
Output
Output
Output
Input
Power
Input
Negative supply pins.
Differential output pairs. LVPECL interface levels.
Differential output pairs. LVPECL interface levels.
Core supply pins.
Output enable. When HIGH, forces true outputs (PCIEXTx) to go
Pulldown LOW and the inverted outputs (PCIEXCx) to go HIGH. When LOW,
outputs are enabled. LVCMOS/LVTTL interface levels.
Differential output pairs. LVPECL interface levels.
Differential output pairs. LVPECL interface levels.
Differential output pairs. LVPECL interface levels.
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Pulldown
Bypass select pin. When HIGH, the PLL is in bypass mode, and the
device can function as a 1:6 buffer. LVCMOS/LVTTL interface levels.
Analog supply pin. Requires 24Ω series resistor.
Pullup Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
23
CLK
Input Pulldown Non-inverting differential clock input.
24
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. V_CC/2 default when left floating.
25
FS0
Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
26, 27
PCIEXT0,
PCIEXC0
Output
Differential output pairs. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
C
IN
R_PULLUP
R_PULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
51
KΩ
51
KΩ
TABLE 3A. RATIO OF OUTPUT FREQUENCY TO
INPUT FREQUENCY FUNCTION TABLE, FS0
Inputs
Outputs
FS0
PCIEX0 PCIEX1 PCIEX2
0
1
5/4
5/4
1
1
1
1
TABLE 3B. RATIO OF OUTPUT FREQUENCY TO
INPUT FREQUENCY FUNCTION TABLE, FS1
Inputs
Outputs
FS1
PCIEX3 PCIEX4 PCIEX5
0
1
1
1
1
5/4
5/4
5/4
TABLE 3C. OUTPUT ENABLE
FUNCTION TABLE, nOE0
Inputs Outputs
nOE0 PCIEX0:2
0
Enabled
1
Disabled
9DB306BL
TABLE 3D. OUTPUT ENABLE
FUNCTION TABLE, nOE1
Inputs Outputs
nOE1 PCIEX3:5
0
Enabled
1
Disabled
TABLE 3E. PLL BANDWIDTH
FUNCTION TABLE
Inputs
Bandwidth
PLL_BW
0
500kHz
1
1MHz
www.icst.com/products/hiperclocks.html
2
TABLE 3F. PLL MODE
FUNCTION TABLE
Inputs
PLL Mode
BYPASS
1
Disabled
0
Enabled
REV. A APRIL 7, 2005