ICS95V842 Datasheet, PDF (8/9 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Clock Driver (60MHz - 220MHz)

ICS95V842
Y_X, FB_OUTC
Y_X, FB_OUTT
Parameter Measurement Information
t(hper_n)
t(hper_n+1)
1
fo
t_{(jit_Hper) =} t_{(jit_Hper_n) -} 1
2xf_O
Figure 7. Half-Period Jitter
80%
Clock Inputs
and Outputs
20%
Rise tsl
Fall tsl
80%
VID, VOD
20%
Figure 8. Input and Output Slew Rates
0830A—09/10/04
8