ICS95V842 Datasheet, PDF (5/9 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Clock Driver (60MHz - 220MHz)

ICS95V842
Switching Characteristics
T_A = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
Max clock frequency³
freq_op
40
Application Frequency
Range³
freq_App
60
Input clock duty cycle
d_tin
40
Input clock slew rate
t_sl(I)
1
CLK stabilization
Low-to high level propagation
delay time
T_STAB
t_PLH1
CLK_IN to any output
High-to low level propagation
delay time
t_PHL1
CLK_IN to any output
Output enable time
t_en
PD# to any output
5
Output disable time
Period jitter
Half-period jitter
t_dis
t_{jit (per)}
t_jit(hper)
PD# to any output
5
-75
-75
Output clock slew rate
Cycle to Cycle Jitter
t_sl(o)
t_cyc-t_cyc
Over the application
1
frequency range
-75
Static Phase Offset
t_(spo)
-50
Output to Output Skew
t_skew
40
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc,
were the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics are guaranteed for application frequency range. The
PLL Locks over the Max Clock Frequency range, but the device doe not
necessarily meet other timing parameters.
4. Does not include jitter.
MAX UNITS
333 MHz
220 MHz
60
%
2
v/ns
100 µs
5.5
ns
5.5
ns
ns
ns
75
ps
75
ps
2.5 v/ns
75
ps
50
ps
60
ps
0830A—09/10/04
5