ICS95V842 Datasheet, PDF (7/9 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Clock Driver (60MHz - 220MHz)

ICS95V842
CLK_INC
CLK_INT
FB_INC
FB_INT
Y_X#
Y_X
Y_X, FB_OUTC
Y_X, FB_OUTT
Y_X, FB_OUTC
Y_X, FB_OUTT
Y_X, FB_OUTC
Y_X, FB_OUTT
0830A—09/10/04
Parameter Measurement Information
t( _{) n}
n=N
t( ₎₌
1 ^t( ) n
N
(N is a large number of samples)
Figure 4. Static Phase Offset
t _{( ) n+1}
t_{(SK_O)}
Figure 5. Output Skew
1
f_O
t_{(jit_per) =} t_{C(n) -}
1
f_O
Figure 6. Period Jitter
7