ICS95V842 Datasheet, PDF (2/9 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Clock Driver (60MHz - 220MHz)

ICS95V842
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
PIN NAME
VDD2.5
DDRT0
DDRC0
GND
CLK_INT
CLK_INC
AVDD
AGND
PIN TYPE
PWR
OUT
OUT
PWR
IN
IN
PWR
PWR
9
FB_OUTC
OUT
10 FB_OUTT
OUT
11
FB_INT
IN
12
FB_INC
13
VDD2.5
14
DDRT1
15
DDRC1
16
GND
IN
PWR
OUT
OUT
PWR
DESCRIPTION
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
"True" reference clock input.
"Complementary" reference clock input.
3.3V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
Complement single-ended feedback output, dedicated external
feedback. It switches at the same frequency as other DDR outputs,
This output must be connect to FB_INC.
True single-ended feedback output, dedicated external feedback. It
switches at the same frequency as other DDR outputs, This output
must be connect to FB_INT.
True single-ended feedback input, provides feedback signal to internal
PLL for synchronization with CLK_INT to eliminate phase error.
Complement single-ended feedback input, provides feedback signal to
internal PLL for synchronization with CLK_INT to eliminate phase
error.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
0830A—09/10/04
2