ICS950403 Datasheet, PDF (8/18 Pages) Integrated Circuit Systems – AMD - K8™ System Clock Chip

ICS950403
Advance Information
I²C Table: Output Control Register
Byte 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
-
-
-
-
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
I²C Table: Watchdog Timer Register
Byte 9
Bit 7
Bit 6
Bit 5
Pin #
-
-
-
Name
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
Type
0
RW
-
RW
-
RW
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
WD4
These bits represent
RW
-
X*290ms the watchdog
WD3
timer will wait before it
RW
-
WD2
goes to alarm mode.
RW
-
WD1
Default is 16 X 290ms
RW
-
WD0
=4.64 seconds
RW
-
1
PWD
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
1
PWD
-
0
-
0
-
0
-
1
-
0
-
0
-
0
-
0
I²C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Pin #
Name
Control
Function
Bit 7
-
M/NEN
M/N Programming
Enable
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
WDEN
WDFSEN
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
Watchdog Enable
WD Safe Frequency
Mode
Writing to these bit will
configure the safe
frequency as Byte0 bit
(5:1)
Type
RW
RW
RW
RW
RW
RW
RW
RW
I²C Table: VCO Frequency Control Register
Byte 11
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
-
-
-
-
Name
N Div8
M Div6
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
Control
Function
N Divider Bit 8
The decimal
representation of M Div
(6:0) + 2 is equal to
reference divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
0732—01/27/03
Type
RW
RW
RW
RW
RW
RW
RW
RW
8
0
Disable
Disable
Latched
FS/Byte0
-
-
-
-
-
1
Enable
Enable
WD B10
b(4:0)
-
-
-
-
-
0
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PWD
0
0
0
0
0
0
0
1
PWD
X
X
X
X
X
X
X
X