ICS950403 Datasheet, PDF (12/18 Pages) Integrated Circuit Systems – AMD - K8™ System Clock Chip

ICS950403
Advance Information
I²C Table: Drive Strength Control Register
Byte 22
Pin #
Name
Control
Function
Type
0
Bit 7
-
PCI9/HTT3 DrCntrl
PCICLK9/HTTCLK3
Drive Strength Control
RW
1X
Bit 6
-
PCI6Drv
PCICLK6 Drive
Strength Control
RW
1X
Bit 5
-
PCI3Drv
PCICLK3 Drive
Strength Control
RW
1X
Bit 4
-
PCI2Drv
PCICLK2 Drive
Strength Control
RW
1X
Bit 3
-
PCIFDrv
PCICLK_F Drive
Strength Control
RW
1X
Bit 2
-
24_48Drv
24_48MHz Drive
Strength Control
RW
1X
Bit 1
-
PCI8/HTT2 DrCntrl
PCICLK8/HTTCLK2
Drive Strength Control
RW
1X
Bit 0
-
PCI7/HTT1 DrCntrl
PCICLK7/HTTCLK1
Drive Strength Control
RW
1X
I²C Table: Slew Rate Control Register
Byte 23
Pin #
Name
Control
Function
Type
0
Bit 7
-
Reserved
Reserved
RW
-
Bit 6
-
Reserved
Reserved
RW
-
Bit 5
-
Reserved
Reserved
RW
-
Bit 4
-
Reserved
Reserved
RW
-
Bit 3
-
PCISlw1
PCICLK(1:0) Slew
RW
-
Bit 2
-
PCISlw0
Rate Control
RW
-
Bit 1
-
PCISlw1
PCICLK(10, 5:4) Slew
RW
-
Bit 0
-
PCISlw0
Rate Control
RW
-
I²C Table: Slew Rate Control Register
Byte 24
Pin #
Name
Control
Function
Type
0
Bit 7
-
REFSlw1
REF(2:0) Slew Rate
RW
-
Bit 6
-
REFSlw0
Control
RW
-
Bit 5
-
48MSlw1
48MHz Slew Rate
RW
-
Bit 4
-
48MSlw0
Control
RW
-
Bit 3
-
Reserved
Reserved
RW
-
Bit 2
-
Reserved
Reserved
RW
-
Bit 1
-
Reserved
Reserved
RW
-
Bit 0
-
Reserved
Reserved
RW
-
1
PWD
2X
1
2X
1
2X
1
2X
1
2X
1
2X
1
2X
1
2X
1
1
PWD
-
1
-
0
-
1
-
0
-
1
-
0
-
1
-
0
1
PWD
-
1
-
0
-
1
-
0
-
1
-
0
-
1
-
1
0732—01/27/03
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