ICS950403 Datasheet, PDF (10/18 Pages) Integrated Circuit Systems – AMD - K8™ System Clock Chip

ICS950403
Advance Information
Table 2: Divider Ratio Combination Table
Divider (3:2)
Bit 00
01
10
11 MSB
1
2
4
8
00 ⁰⁰⁰⁰ 2 ⁰¹⁰⁰ 4 ¹⁰⁰⁰ 8 ¹¹⁰⁰ 16
01 0001 3 0101 6 1001 12 1101 24
10 0010 5 0110 10 1010 20 1110 40
11 0011 7 0111 14 1011 28 1111 56
LSB ^{Address Div Address Div Address Div Address Div}
I²C Table: Output Divider Control Register
Byte 16
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I²C Table: Output Divider Control Register
Byte 17
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Reserved
Reserved
Reserved
CPUINV
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
CPU Phase Invert
Reserved
Reserved
Reserved
Reserved
I²C Table: Group Skew Control Register
Byte 18
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Reserved
Reserved
Reserved
Reserved
CPUSkw3
CPUSkw2
CPUSkw1
CPUSkw0
Control
Function
Reserved
Reserved
Reserved
Reserved
All other clocks -
CPUCLKT/C Skew
Control
Type
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
1
PWD
-
X
-
X
-
X
-
X
-
X
-
X
-
X
-
X
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
Default
-
-
-
-
1
-
-
-
Inverse
-
-
-
-
PWD
X
X
X
X
X
X
X
X
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
-
-
-
-
-
-
-
-
See Table 3: 7-Steps Skew
Programming Table
PWD
0
0
0
0
0
0
0
0
0732—01/27/03
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