ICS93V855 Datasheet, PDF (8/9 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Clock Driver

ICS93V855
Y_X, FB_OUTC
Y_X, FB_OUTT
Parameter Measurement Information
tjit(hper_n)
tjit(hper_n+1)
1
fo
t_jit(hper)
=
t
jit(hper_n)
-
1
2xf_O
Figure 7. Half-Period Jitter
80%
Clock Inputs
and Outputs
20%
tslr
80%
VID, VOD
20%
tslf
Figure 8. Input and Output Slew Rates
0497B—06/01/04
8