ICS93V855 Datasheet, PDF (1/9 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Clock Driver

Integrated
Circuit
Systems, Inc.
ICS93V855
DDR Phase Lock Loop Clock Driver
Recommended Application:
DDR Clock Driver
Product Description/Features:
• Low skew, low jitter PLL clock driver
• External feedback pins for input to output
synchronization
• Spread Spectrum tolerant inputs
• With bypass mode mux
• Operating frequency 60 to 170 MHz
Switching Characteristics:
• CYCLE - CYCLE jitter:<75ps
• OUTPUT - OUTPUT skew: <60ps
• Output Rise and Fall Time: 650ps - 950ps
Pin Configuration
GND 1
DDRC0 2
DDRT0 3
VDD2.5 4
CLK_INT 5
CLK_INC 6
AVDD2.5 7
AGND 8
GND 9
DDRC1 10
DDRT1 11
VDD2.5 12
DDRT2 13
DDRC2 14
28 DDRC4
27 DDRT4
26 VDD2.5
25 GND
24 FB_OUTC
23 FB_OUTT
22 VDD2.5
21 FB_INT
20 FB_INC
19 GND
18 VDD2.5
17 DDRT3
16 DDRC3
15 GND
28-Pin 4.4mm TSSOP
Block Diagram
Control
Logic
FB_INT
FB_INC
CLK_INC
PLL
CLK_INT
AVDD2.5
0497B—06/01/04
FB_OUTT
FB_OUTC
DDRT0
DDRC0
DDRT1
DDRC1
DDRT2
DDRC2
DDRT3
DDRC3
DDRT4
DDRC4
Functionality
INPUTS
OUTPUTS
AVDD CLK_INT CLK_INC DDRT DDRC FB_OUTT FB_OUTC
GND
L
H
L
H
L
H
GND H
L
H
L
H
L
2.5V
(nom)
L
H
L
H
L
H
2.5V
(nom)
H
L
H
L
H
L
2.5V
(nom)
<20 MHz
<20 MHz
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PLL State
Bypassed/Off
Bypassed/Off
On
On
Off