ICS93V855 Datasheet, PDF (4/9 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Clock Driver

ICS93V855
DC Electrical Characteristics
TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
V_DDQ, A_VDD
2.3
2.5
2.7
V
Low level input voltage
V_IL
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.4 V_DD/2 - 0.18 V
High level input voltage
V_IH
CLK_INT, CLK_INC, FB_INC,
FB_INT
V_DD/2 + 0.18
2.1
V
DC input signal voltage (note
1,2)
V_IN
-0.3
V_DD + 0.3
V
Differential input signal
voltage (note 3)
V_ID
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.36
V_DD + 0.6
V
Differential output voltage
(note 3)
V_OD
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.7
V_DD + 0.6
V
Output differential cross-
voltage (note 4)
V_OX
V_DD/2 - 0.15
V_DD/2 + 0.15 V
Input differential cross-
voltage (note 4)
V_IX
V_DD/2 - 0.2 V_DD/2 V_DD/2 + 0.2
V
Operating free-air
temperature
T_A
0
85
°C
Notes:
1 Unused inputs must be held high or low to prevent them from floating.
2 DC input signal voltage specifies the allowable DC excursion of differential input.
3 Differential input signal voltage specifies the differential voltage [VTR-VCP] required for switching,
where VTR is the true input level and VCP is the complementary input level.
4 Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the
differential signal must be crossing.
0497B—06/01/04
4