ICS93V855 Datasheet, PDF (5/9 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Clock Driver

ICS93V855
Switching Characteristics
T_A = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
Max clock frequency³
freq_op
33
Application Frequency
Range³
freq_App
60
Input clock duty cycle
Input clock slew rate
CLK stabilization
Low-to high level propagation
delay time
d_tin
t_sl(I)
T_STAB
t_PLH1
CLK_IN to any output
40
1
5.5
High-to low level propagation
delay time
t_PHL1
CLK_IN to any output
5.5
Output enable time
Output disable time
Period jitter
t_en
t_dis
t_{jit (per)}
PD# to any output
PD# to any output
5
5
-75
Half-period jitter
Output clock slew rate
Cycle to Cycle Jitter
Phase error⁴
t_jit(hper)
t_sl(o)
t_cyc-t_cyc
t_{(phase error)}
Over the application
frequency range
-100
1
-75
-50
Output to Output Skew
t_skew
40
Rise Time, Fall Time
t_r, t_f
Load = 120Ω/16pF
650
800
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc,
were the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics are guaranteed for application frequency range. The PLL
Locks over the Max Clock Frequency range, but the device doe not necessarily
meet other timing parameters.
4. Does not include jitter.
MAX UNITS
233 MHz
170 MHz
60
%
2
v/ns
100 µs
ns
ns
ns
ns
75
ps
100 ps
2
v/ns
75
ps
50
ps
60
ps
950 ps
0497B—06/01/04
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