ICS9250-32 Datasheet, PDF (8/11 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PII/III™

ICS9250-32
Electrical Characteristics - SDRAM
T_A = 0 - 70C; V_DD = 3.3 V +/-5%; C_L = 20-30 pF (unless otherwise specified)
PARAMETER
Output Impedance¹
Output Impedance¹
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time¹
Fall Time¹
Duty Cycle¹
Skew (ouput to output)¹
Skew (Buffer In to output)¹
SYMBOL
R_DSP2A
R_DSN2A
V_OH2A
V_OL2A
I_OH2A
I_OL2A
t_r2A
t_f2A
d_t2A
t_sk2A
t_sk2B
CONDITIONS
V_O = V_DD*(0.5)
V_O = V_DD*(0.5)
I_OH = -1 mA
I_OL = 1 mA
V_{OH @ MIN} = 2.0 V
V_{OH @ MAX} = 3.135 V
V_{OL @ MIN} = 1.0 V
V_{OL @ MAX} = 0.4 V
V_OL = 0.4 V, V_OH = 2.4 V
V_OH = 2.4 V, V_OL = 0.4 V
V_T = 1.5 V
V_T = 1.5 V
V_T = 1.5 V
MIN TYP MAX UNITS
8.5 10.1 24
Ω
8.5
12
24
Ω
2.4 3.3
V
0.006 0.4 V
-100 -54 _mA
-46 -13
53
90
mA
40
54
0.4
1
1.6 ns
0.4 0.8 1.6 ns
45
51
55
%
212 250 ps
5.5 6.5 7.5 ns
1_{Guaranteed by design, not 100% tested in production.}
AC timing of the t_rise & t_fall is controlled by pre-driver circuit which allows lower impedance output to stay in the middle of
transition time target.
Electrical Characteristics - REF
T_A = 0 - 70C; V_DD = 3.3 V +/-5%; C_L = 10-15 pF (unless otherwise specified)
PARAMETER
Output Impedance¹
Output Impedance¹
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time¹
Fall Time¹
Duty Cycle¹
Jitter, Cycle-to-cycle¹
SYMBOL
R_DSP5
R_DSN5
V_OH5
V_OL5
I_OH5
I_OL5
t_r5
t_f5
d_t5
t_jcyc-cyc5
CONDITIONS
V_O = V_DD*(0.5)
V_O = V_DD*(0.5)
I_OH = -1 mA
I_OL = 1 mA
V_{OH @ MIN} = 2.0 V
V_{OH @ MAX} = 3.135 V
V_{OL @ MIN} = 1.0 V
V_{OL @ MAX} = 0.4 V
V_OL = 0.4 V, V_OH = 2.4 V
V_OH = 2.4 V, V_OL = 0.4 V
V_T = 1.5 V
V_T = 1.5 V, CPU=66,100,133 MHz
MIN TYP MAX UNITS
16
24
60
Ω
16 19.2 60
Ω
2.4 3.3
V
0.014 0.4 V
-65 -27
mA
-23
-8
29
65
mA
21
27
1.4
4
ns
1.4
4
ns
45
54
55
%
674 1000 ps
1_{Guaranteed by design, not 100% tested in production.}
AC timing of the t_rise & t_fall is controlled by pre-driver circuit which allows lower impedance output to stay in the middle of
transition time target.
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