ICS9250-32 Datasheet, PDF (1/11 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PII/III™

Integrated
Circuit
Systems, Inc.
ICS9250-32
Frequency Generator & Integrated Buffers for PII/III™
Recommended Application:
Timna Style Chipset
Output Features:
• 3 - CPUs @ 2.5V
• 8 - PCI @ 3.3V
• 2 - IOAPIC @ 2.5V
• 1 - MREF @ 2.5V, DRCG memory reference clock
• 9 - SDRAM @ 3.3V including one free running
• 1 - 2V48M @ 2.5V fixed (DOT)
• 1 - 3V48M @ 3.3V fixed (USB)
• 2 - REF @ 3.3V, 14.318MHz.
Features:
• Support power management: CPU, PCI, SDRAM stop
from I²C programming.
• Spread spectrum for EMI control (0 to -0.5%)
• Uses external 14.318MHz crystal
Key Specifications:
• CPU Output Jitter _(Cyc-Cyc): <175ps
• IOAPIC Output Jitter _(Cyc-Cyc): <500ps
• MREF Output Jitter _(Cyc-Cyc): <250ps
• 2V48M Output Jitter (Cyc-Cyc): <250ps
• 3V48M Output Jitter (Cyc-Cyc): <500ps
• CPU - CPU: < 175ps
• SDRAM - SDRAM < 250ps
• PCI - PCI: < 500ps
• IOAPIC - IOAPIC: < 250ps
• BUFFER_IN to SDRAM prop delay: 5.5 to 7.5ns
Block Diagram
PLL2
X1
X2
BUF_IN
CPU_EN#
SDATA
SCLK
FS (1:0)
XTAL
OSC
PLL1
Spread
Spectrum
Control
Logic
Config.
Reg.
CPU
DIVDER
SDRAM
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
3V48M
2V48M
REF (1:0)
2
CPUCLK (2:0)
3
SDRAM (7:0)
8
SDRAM_F
IOAPIC (1:0)
2
PCICLK (7:0)
8
MREF66
9250-32 Rev B 9/7/00
Third party brands and names are the property of their respective owners.
Pin Configuration
2V48M
1
3V48M
2
VDD48
3
GND48
4
X1
5
X2
6
GND
7
*(CPU2_EN#)REF0
8
REF1
9
VDD
10
PCICLK0
11
PCICLK1
12
GNDPCI
13
VDDPCI
14
PCICLK2
15
PCICLK3
16
PCICLK4
17
PCICLK5
18
VDDPCI
19
GNDPCI
20
PCICLK6
21
PCICLK7
22
SCLK
23
VDDA
24
GNDA
25
SDATA
26
BUF_IN
27
*FS0
28
56
VDDLIOAPIC
55
IOAPIC0
54
IOAPIC1
53
GNDLIOAPIC
52
VDDLCPU
51
CPUCLK0
50
CPUCLK1
49
VDDLCPU
48
GNDLCPU
47
CPUCLK2
46
MREF66
45
VDD
44
SDRAM_F
43
SDRAM0
42
VDDSDR
41
GNDSDR
40
SDRAM1
39
SDRAM2
38
SDRAM3
37
GNDSDR
36
VDDSDR
35
SDRAM4
34
SDRAM5
33
VDDSDR
32
GNDSDR
31
SDRAM6
30
SDRAM7
29
FS1*
56-Pin 300mil SSOP
* These inputs have a 50K pull up to VDD.
Functionality
FS1
FS0
Power up Latched
REF1/CPU2_EN#
CPU0
CPU1,
MREF
11
1
66MHz
11
0
66MHz
10
X
TCLK/2
01
X
Reserved
00
X
Tristate
CPU2
Tristate
66MHz
TCLK/2
Reserved
Tristate
Power Groups
VDD = REF, X1, X2
VDDPCI = PCICLK
VDDSDR = SDRAM
VDD48 = 3V48M
VDDLCPU = CPU
VDDLIOAPIC = IOAPIC, 2V48M
VDDA = PLL Core
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.