ICS9250-32 Datasheet, PDF (6/11 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PII/III™

ICS9250-32
Electrical Characteristics - CPU
T_A = 0 - 70C; V_DDL = 2.5 V +/-5%; C_L = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output Impedance¹
Output Impedance¹
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time¹
Fall Time¹
Duty Cycle¹
R_DSP2B
R_DSN2B
V_OH2B
V_OL2B
I_OH2B
I_OL2B
t_r2B
t_f2B
d_t2B
V_O = V_DD*(0.5)
V_O = V_DD*(0.5)
I_OH = -1 mA
I_OL = 1 mA
V_{OH @ MIN} = 1.0 V
V_{OH @ MAX} = 2.375 V
V_{OL @ MIN} = 1.2 V
V_{OL @ MAX} = 0.3 V
V_OL = 0.4 V, V_OH = 2.0 V
V_OH = 2.0 V, V_OL = 0.4 V
V_T = 1.25 V
11.5 14
45
Ω
11.5 16
45
Ω
2
2.5
V
0.011 0.4 V
-79
-27 _mA
-27 -10
27
66
mA
20
30
0.4 1.1 1.6 ns
0.4 1.1 1.6 ns
45
47
55
%
Skew window¹
Jitter, Cycle-to-cycle¹
t_sk2B
t_jcyc-cyc2B
V_T = 1.25 V
V_T = 1.25 V
54 175 ps
140 250 ps
1_{Guaranteed by design, not 100% tested in production.}
AC timing of the t_rise & t_fall is controlled by pre-driver circuit which allows lower impedance output to stay in the middle of
transition time target.
Electrical Characteristics - PCI
T_A = 0 - 70C; V_DD = 3.3 V +/-5%; C_L = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Impedance¹
Output Impedance¹
R_DSP1B
R_DSN1B
V_O = V_DD*(0.5)
V_O = V_DD*(0.5)
Output High Voltage
V_OH1 I_OH = -1 mA
Output Low Voltage
V_OL1
I_OL = 1 mA
Output High Current
I_OH1
V_{OH @ MIN} = 1.0 V
V_{OH @ MAX} = 3.135 V
Output Low Current
Rise Time¹
Fall Time¹
Duty Cycle¹
Skew window¹
Jitter, Cycle-to-cycle¹
I_OL1
t_r1
t_f1
d_t1
t_sk1
t_jcyc-cyc1
V_{OL @ MIN} = 1.95 V
V_{OL @ MAX} = 0.4 V
V_OL = 0.4 V, V_OH = 2.4 V
V_OH = 2.4 V, V_OL = 0.4 V
V_T = 1.5 V
V_T = 1.5 V
V_T = 1.5 V
1_{Guaranteed by design, not 100% tested in production.}
MIN TYP MAX UNITS
11
14
55
Ω
11
13
55
Ω
2.4 3.29
V
0.009 0.55 V
-111 -29
mA
-27 -12
29
96
mA
31
27
0.5 1.2
2
ns
0.5 1.4
2
ns
45
51
55
%
212 500 ps
230 500 ps
AC timing of the t_rise & t_fall is controlled by pre-driver circuit which allows lower impedance output to stay in the middle of
transition time target.
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