ICS9250-32 Datasheet, PDF (2/11 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PII/III™

ICS9250-32
General Description
The ICS9250-32 is the single chip clock solution for Desktop designs. It provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I²C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-32 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Serial programming I²C interface allows changing functions, stop clock programming and frequency selection.
Pin Configuration
PIN NUMBER
1
2
3, 10, 14, 19, 24,
33, 36, 42, 45
4, 7, 13, 20, 25,
32, 37, 41, 48, 53
5
6
PIN NAME
2V48M
3V48M
VDD
GND
X1
X2
8
9
22, 21, 18, 17, 16,
15, 12, 11
23
26
27
28
29
30, 31, 34, 35, 38,
39, 40, 43
44
46
49, 52, 56
47, 50, 51
54, 55
CPU2_EN#
REF0
REF1
PCICLK (7:0)
SCLK
SDATA
BUF_IN
FS0
FS1
SDRAM (7:0)
SDRAM_F
MREF66
VDDL
CPUCLK (2:0)
IOAPIC (1:0)
TYPE
OUT
OUT
PWR
PWR
IN
OUT
IN
OUT
OUT
OUT
IN
I/O
IN
IN
IN
OUT
OUT
OUT
PWR
OUT
OUT
DESCRIPTION
48MHz output clock 2.5V (DOT) clock
48MHz output clock 3.3V (USB) clock
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 3V48 output
Ground pins
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Disables CPU2 when pulled high (default)
Enables CPU2 when pulled Low
14.318 MHz reference clock.
14.318 MHz reference clock.
PCI clock outputs.
Clock pin of I²C circuitry 5V tolerant
Data pin for I²C circuitry 5V tolerant
Input to fan out buffer for SDRAM
Frequency select pin.
Frequency select pin.
SDRAM clock outputs
SDRAM clock output free running not affected by I²C
DRCG reference memory 2.5V 66MHz
Power pins for CPUCLKs, and IOAPIC clocks. 2.5V
2.5V CPU clock outputs.
2.5V IOAPIC clock outputs
Functionality
FS1
FS0
Power up Latched CPU0
REF1/CPU2_EN# CPU1,MREF
CPU2
1
1
1
66MHz
Tristate
1
1
0
66MHz
66MHz
10
X
TCLK/2 TCLK/2
0
1
X
Reserved Reserved
0
0
X
Tristate
Tristate
SDRAM
[0:7]
BUF_IN
BUF_IN
BUF_IN
Reserved
Tristate
2V48:
3V48
48MHz
48MHz
TCLK/2
Reserved
Tristate
PCI
REF
IOAPIC
33MHz
33MHz
TCLK/4
Reserved
Tristate
14.318MHz
14.318MHz
TCLK
Reserved
Tristate
33MHz
33MHz
TCLK/4
Reserved
Tristate
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