ICS813001I Datasheet, PDF (8/18 Pages) Integrated Circuit Systems – DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK-TM PLL

Integrated
Circuit
Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS813001I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V_CC, V_CCA, and V_CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each V .
CCA
3.3V or 2.5V
V_CC
.01μF 10Ω
V
CCA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF
single ended levels. The reference voltage V_REF = V_CC/2 is in the center of the input voltage swing. For example, if the
generated by the bias resistors R1, R2 and C1. This bias circuit input clock swing is only 2.5V and V_CC = 3.3V, V_REF should be
should be located as close as possible to the input pin.The ratio 1.25V and R2/R1 = 0.609.
VCC
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLK
nCLK
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
813001AGI
www.icst.com/products/hiperclocks.html
8
REV. A SEPTEMBER 2, 2005