ICS813001I Datasheet, PDF (5/18 Pages) Integrated Circuit Systems – DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK-TM PLL

Integrated
Circuit
Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
TABLE 5A. AC CHARACTERISTICS, V_CC = V_CCA = V_CCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
f_OUT
tjit(Ø)
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
VCO_SEL = 1
622.08MHz (12kHz - 20MHz)
40.83
f_VCO
t_R / t_F
odc
PLL VCO Lock Range
Output Rise/Fall Time
Output Duty Cycle
490
20% to 80%
250
N÷1
43
N ≠ ÷1
48
NOTE 1: Phase jitter using a crystal interface.
Typical
0.84
Maximum Units
640
MHz
ps
640
MHz
500
ps
57
%
52
%
TABLE 5B. AC CHARACTERISTICS, V_CC = V_CCA = 3.3V±5%, V_CCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
f_OUT
tjit(Ø)
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
VCO_SEL = 1
40.83
622.08MHz (12kHz - 20MHz)
0.87
f_VCO
t_R / t_F
odc
PLL VCO Lock Range
Output Rise/Fall Time
Output Duty Cycle
490
20% to 80%
250
N÷1
43
N ≠ ÷1
48
NOTE 1: Phase jitter using a crystal interface.
Maximum Units
640
MHz
ps
640
MHz
500
ps
57
%
52
%
TABLE 5C.
AC
CHARACTERISTICS,
V=
CC
V=
CCA
V
CCO
= 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
f_OUT
tjit(Ø)
f_VCO
t_R / t_F
odc
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
PLL VCO Lock Range
Output Rise/Fall Time
Output Duty Cycle
NOTE 1: Phase jitter using a crystal interface.
VCO_SEL = 1
622.08MHz (12kHz - 20MHz)
20% to 80%
N÷1
N ≠ ÷1
40.83
490
250
43
48
Typical
1.2
Maximum Units
640
MHz
ps
640
MHz
500
ps
57
%
52
%
813001AGI
www.icst.com/products/hiperclocks.html
5
REV. A SEPTEMBER 2, 2005