ICS813001I Datasheet, PDF (1/18 Pages) Integrated Circuit Systems – DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK-TM PLL

Integrated
Circuit
Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
GENERAL DESCRIPTION
FEATURES
ICS
HiPerClockS™
The ICS813001I is a dual VCXO + FemtoClock™
Multiplier designed for use in Discrete PLL
loops. Two selectable external VCXO crystals
allow the device to be used in multi-rate appli-
cations, where a given line card can be
• One 3.3V or 2.5V LVPECL output pair
• Two selectable crystal oscillator interfaces for the VCXO,
one differential clock or one LVCMOS/LVTTL clock inputs
• CLK1/nCLK1 supports the following input types:
switched, for example, between 1Gb Ethernet (125MHz ^{LVPECL, LVDS, LVHSTL, SSTL, HCSL}
system reference clock) and 1Gb Fibre Channel
(106.25MHz system reference clock) modes. Of course,
a multitude of other applications are also possible such
• Crystal operating frequency range: 14MHz - 24MHz
• VCO range: 490MHz - 640MHz
as switching between 74.25MHz and 74.175824MHz
for HDTV, switching between SONET, FEC and non FEC
rates, etc.
The ICS813001I is a two stage device – a VCXO followed
by a FemtoClock PLL. The FemtoClock PLL can multiply
the crystal frequency of the VCXO to provide an output
frequency range of 40.83MHz to 640MHz, with a random
rms phase jitter of less than 1ps (12kHz – 20MHz). This
phase jitter performance meets the requirements of 1Gb/
10Gb Ethernet, 1Gb, 2Gb, 4Gb and 10Gb Fibre Channel,
and SONET up to OC48. The FemtoClock PLL can also be
bypassed if frequency multiplication is not required. For
testing/debug purposes, de-assertion of the output enable
pin will place both Q and nQ in a high impedance state.
BLOCK DIAGRAM
• Output frequency range: 40.83MHz - 640MHz
• VCXO pull range: ±100ppm (typical)
• Supports the following applications (among others):
SONET, Ethernet, Fibre Channel, HDTV, MPEG
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.84 (typical)
• Supply voltage modes:
V_CC/V_CCO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both, Standard and RoHS/Lead-Free
compliant packages
VCO_SEL ^Pullup
CLK_SEL0 ^Pulldown
CLK_SEL1 ^Pullup
CLK0 ^Pulldown
CLK1 ^Pulldown
nCLK1 ^Pullup
XTAL_IN0
XTAL_OUT0
XTAL_IN1
XTAL_OUT1
VC
M2 ^Pullup
M1 ^Pulldown
M0 ^Pulldown
N2 ^Pulldown
N1 ^Pullup
N0 ^Pullup
OE ^Pullup
813001AGI
00
01
10
(default)
VCXO
11
0
VCO
PD
490-640MHz ¹
Feedback Divider M
M2:M0
000 ÷16
001 ÷20
010 ÷22
011 ÷24
100 ÷25 (default)
101 ÷32
110 ÷40
111 MR
Output Divider N
N2:N0
000 ÷1
001 ÷2
010 ÷3
011 ÷4 (default)
100 ÷5
101 ÷6
110 ÷8
111 ÷12
www.icst.com/products/hiperclocks.html
1
Q
nQ
PIN ASSIGNMENT
VCO_SEL 1
N0 2
N1 3
N2 4
VCCO 5
Q6
nQ 7
VEE 8
VCCA 9
VCC 10
XTAL_OUT1 11
XTAL_IN1 ¹²
24 CLK_SEL1
23 CLK_SEL0
22 OE
21 M2
20 M1
19 M0
18 CLK1
17 nCLK1
16 ^CLK0
15 VC
14 XTAL_IN0
13 XTAL_OUT0
ICS813001I
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
REV. A SEPTEMBER 2, 2005