ICS813001I Datasheet, PDF (10/18 Pages) Integrated Circuit Systems – DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK-TM PLL

Integrated
Circuit
Systems, Inc.
TABLE 7. VARACTOR PARAMETERS
Symbol
C_{V_LOW}
C_{V_HIGH}
Parameter
Low Varactor Capacitance
High Varactor Capacitance
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Test Conditions
V_C = 0V
V_C = 3.3V
Minimum
Typical
15
27.4
Maximum
Units
pF
pF
FORMULAS
(( )) ^{(( )) CLow =}
C_L1 + C_S1 + C_{V _ Low} ⋅ C_L2 + C_{S 2} + C_{V _ Low}
C_L1 + C_S1 + C_{V _ Low} + C_L2 + C_{S 2} + C_{V _ Low}
(( )) ^{(( )) CHigh =}
C_L1 + C_S1 + C_{V _ High} ⋅ C_L2 + C_{S 2} + C_{V _ High}
C_L1 + C_S1 + C_{V _ High} + C_L2 + C_{S 2} + C_{V _ High}
• C_Low is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance.
C determines the high frequency component on the TPR.
Low
• C_High is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance.
C determines the low frequency component on the TPR.
High
⎜⎛
⎟⎞
Total
Pull
Range
(TPR
)
=
⎜
⎜
⎜
⎝
2
⋅
C
0
C1
⋅
1
⎜⎝⎛^{1 +}
C
Low
C
0
⎟⎠⎞
−
1
2
⋅
C
0
C1
⋅
⎜⎛1
⎝
+
C
High
C
0
⎟⎞
⎠
⎟
⎟
⎟
⎠
⋅
10
6
Absolute Pull Range (APR) = Total Pull Range – (Frequency Tolerance + Frequency Stability + Aging)
EXAMPLE CALCULATIONS
Using the tables and figures above, we can now calculate the
TPR and APR of the VCXO using the example crystal
parameters. For the numerical example below there were
some assumptions made. First, the stray capacitance (C_S1,
C_S2), which is all the excess capacitance due to board
parasitic, is 4pF. Second, the expected lifetime of the project
is 5 years; hence the inaccuracy due to aging is ±15ppm.
Third, though many boards will not require load tuning
capacitors (C_L1, C_L2), it is recommended for long-term
consistent performance of the system that two tuning
capacitor pads be placed into every design. Typical values
for the load tuning capacitors will range from 0 to 4pF.
(0 + 4pƒ + 15pƒ ) · (0 + 4pƒ + 15pƒ )
C_Low = _{(0 + 4pƒ + 15pƒ ) · (0 + 4pƒ + 15pƒ )} = 9.5pƒ
(0 + 4pƒ + 27.4pƒ ) · (0 + 4pƒ + 27.4pƒ )
C=
High _{(0 + 4pƒ + 27.4pƒ ) · (0 + 4pƒ + 27.4pƒ )}
= 15.7pƒ
TPR =
1
1
⎟⎞
( ) ( ) ^–
⎟ ⋅ 1^{= · 106 · = 212ppm}
2· 220 · 1 + ^9.5pƒ _4pƒ
2· 220 · 1 +15.7^pƒ _4pƒ ⎟⎠⎞ _{⎟⎟âŽ} 
TPR = ±106ppm
APR = 106ppm – (20ppm + 20ppm + 15ppm) = ±51ppm
The example above will ensure a total pull range of
±106 ppm with an APR of ±51ppm. Many times, board
designers may select their own crystal based on their
application. If the application requires a tighter APR, a crystal
with better pullability (C0/C1 ratio) can be used. Also, with the
equations above, one can vary the frequency tolerance,
temperature stability, and aging or shunt capacitance to
achieve the required pullability.
813001AGI
www.icst.com/products/hiperclocks.html
10
REV. A SEPTEMBER 2, 2005