ICS813001I Datasheet, PDF (2/18 Pages) Integrated Circuit Systems – DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK-TM PLL

Integrated
Circuit
Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
TABLE 1. PIN DESCRIPTIONS
Νυμ βε ρ
Ναμ ε
Τψπε
Δ ε σχριπτιον
1
VCO_SEL Input Pullup VCO select pin. LVCMOS/LVTTL interface levels.
2, 3
N0, N1
Input Pullup _{Output divider select pins. Default value = ÷4.}
4
N2
Input Pulldown ^{LVCMOS/LVTTL interface levels.}
5
V_CCO
Power
6, 7
Q, nQ
Ouput
Output supply pin.
Differential output pair. LVPECL interface levels.
8
V_EE
Power
9
V_CCA
Power
10
V
Power
CC
11
12
XTAL_OUT1,
XTAL_IN1
Input
13
14
XTAL_OUT0,
XTAL_IN0
Input
Negative supply pin.
Analog supply pin.
Core supply pin.
Parallel resonant crystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
Parallel resonant crystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
15
VC
Input
VCXO control voltage input.
16
CLK0
Input Pulldown LVCMOS/LVTTL clock input.
17
nCLK1
Input Pullup Inverting differential clock input.
18
CLK1
Input Pulldown Non-inverting differential clock input.
19, 20
21
22
M0, M1
M2
OE
Input
Input
Input
Pulldown _{Feedback divider select pins. Default value = ÷25.}
Pullup ^{LVCMOS/LVTTL interface levels.}
Pullup
Output enable. When HIGH, the output is active. When LOW, the output
is in a high impedance state. LVCMOS/LVTTL interface levels.
23
CLK_SEL0 Input Pulldown
Clock select pin. LVCMOS/LVTTL interface levels. Refer to Table 3.
24
CLK_SEL1 Input Pullup
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLDOWN
R_PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3. CONTROL INPUT FUNCTION TABLE
CLK_SEL1
0
0
1
1
Inputs
CLK_SEL0
0
1
0
1
Selected Input
CLK0
CLK1, nCLK1
XTAL0
XTAL1
813001AGI
www.icst.com/products/hiperclocks.html
2
REV. A SEPTEMBER 2, 2005