ICS950218 Datasheet, PDF (7/19 Pages) Integrated Circuit Systems – Programmable Timing Control Hub TM for P4 TM

Integrated
Circuit
Systems, Inc.
ICS950218
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Bit7 45,44
1 CPUT/C2
Bit6 38,37
1 CPUT/C1
Bit5 41,40
1 CPUT/C0
Bit4
-
X FS4 Read back
Bit3
-
X FS3 Read back
Bit2
-
X FS2 Read back
Bit1
-
X FS1 Read back
Bit0
-
X FS0 Read back
Description
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Bit7
-
1 Reserved
Bit6
17
1 PCICLK_9
Bit5
16
1 PCICLK_8
Bit4
15
1 PCICLK_7
Bit3
14
1 PCICLK_6
Bit2
12
1 PCICLK_5
Bit1
11
1 PCICLK_4
Bit0
10
1 PCICLK_3
Description
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
Bit7
23
1 24_48MHz
Bit6
22
1 48MHz
Bit5
-
1 Reset gear shift detect 1 = Enable, 0 = Disable
Bit4
-
0 0 = Sel 48_24# by hardware;1 = I²C
Bit3
-
0 Sel 48_24#, 0 = 24MHz, 1 = 48MHz
Bit2
8
1 PCICLK_2
Bit1
7
1 PCICLK_1
Bit0
6
1 PCICLK_0
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
-
31
30
48
1
27
28
PWD
X
X
1
1
1
1
1
1
MultiSEL0 (read back)
MultiSEL1 (Read back)
3V66_0
3V66_1
REF0
REF1
3V66_48MHz
3V66_2
Description
Notes:
1. PWD = Power on Default
2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
0466B—03/17/04
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