ICS950218 Datasheet, PDF (13/19 Pages) Integrated Circuit Systems – Programmable Timing Control Hub TM for P4 TM

Integrated
Circuit
Systems, Inc.
ICS950218
Byte 23: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
Reserved
48MHz Slew 1
48MHz Slew 0
24_48MHz Slew 1
24_48MHz Slew 0
PWD
X
X
1
0
1
0
1
0
Description
Reserved
48MHz clock slew rate control bits.
01 = strong: 11 = normal; 10 = weakk
24_48MHz clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Operating Supply
Current
V_IH
V_IL
I_IH
I_IL1
I_IL2
I_DD3.3OP1
I_DD3.3OP2
I_DD3.3OP3
V_IN = V_DD
V_IN = 0 V; Inputs with no pull-up resistors
V_IN = 0 V; Inputs with pull-up resistors
C_L = 0pF; Select @ 66 MHz
C_L = Full load; Select @ 100 MHz
C_L =Full load; Select @ 133 MHz
2
V_SS - 0.3
-5
V_DD + 0.3 V
0.8
V
5
-5
µΑ
-200
90
100
230 360
233
360
mA
Powerdown Current I_DD3.3PD
IREF=5 mA
Input Frequency
F_i
V_DD = 3.3 V
Pin Inductance
L_pin
C_IN
Logic Inputs
Input Capacitance¹
C_OUT
Output pin capacitance
C_INX
X1 & X2 pins
Transition time¹
T_trans
To 1st crossing of target frequency
Settling time¹
Clk Stabilization¹
T_s
T_STAB
From 1st crossing to 1% target frequency
From V_DD = 3.3 V to 1% target frequency
Delay¹
t_PZH,t_PZL
t_PHZ,t_PLZ
Output enable delay (all outputs)
Output disable delay (all outputs)
1_{Guaranteed by design, not 100% tested in production.}
38.1
45
14.32
7
5
6
27
36
45
3
3
1
3
1
10
1
10
MHz
nH
pF
pF
pF
ms
ms
ms
ns
ns
0466B—03/17/04
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