ICS950218 Datasheet, PDF (3/19 Pages) Integrated Circuit Systems – Programmable Timing Control Hub TM for P4 TM

Integrated
Circuit
Systems, Inc.
ICS950218
Pin Description
PIN NUMBER
1
2, 9, 18, 24,
32, 39, 46
3
4
5, 13, 21, 29,
36, 43, 47
6
7
PIN NAME
MULTSEL1
REF1
VDD
X1
X2
GND
FS2
PCICLK0
FS3
PCICLK1
SEL 48_24#
8
PCICLK2
FS4
10
PCICLK3
17, 16, 15, 14, 12, 11 PCICLK (9:4)
19
Vtt_PWRGD#
20
28, 30, 31
22
23
25
26
27
33
34
35
RESET#
3V66 (2:0)
FS0
48MHz
FS1
24_48MHz
SDATA
SCLK
SEL66_48#
3V66_48MHz
GND
AVDD
I REF
42
44, 40, 37
45, 41, 38
48
PD#
CPUCLKC (2:0)
CPUCLKT (2:0)
MULTSEL0
REF0
TYPE
DESCRIPTION
IN 3.3V LVTTL input for selecting the current multiplier for CPU outputs.
OUT 3.3V, 14.318MHz reference clock output.
PWR 3.3V power supply
IN Crystal input, has internal load cap (33pF) and feedback resistor from X2
OUT Crystal output, nominally 14.318MHz. Has internal load cap (33pF)
PWR Ground pins for 3.3V supply
IN
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
I/O
IN
IN
OUT
PWR
PWR
OUT
IN
OUT
OUT
IN
OUT
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock output
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock output
This selects the frequency for the 24.48 MHz output. High = 48MHz,
Low=24MHz
3.3V PCI clock output
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock output
3.3V PCI clock outputs
This 5V tolerant LVTTL input is a level sensitive strobe used to determine when FS
(4:0) and MULTISEL inputs are valid and are ready to be sampled
(active low)
Real time system reset signal for frequency value or watchdog timmer timeout.
This signal is active low.
3.3V Fixed 66MHz clock outputs for HUB
Logic input frequency select bit. Input latched at power on.
3.3V Fixed 48MHz clock output.
Logic input frequency select bit. Input latched at power on.
Selectable 24 or 48MHz output.
Data pin for I²C circuitry 5V tolerant
Clock pin for I²C circuitry 5V tolerant
This selects the frequency for the 3V6_48 MHz output High = 66MHz,
Low=48MHz
Selectable 66 or 48MHz output
Ground for CORE PLL
Power for CORE PLL 3.3V nominal
This pin establishes the reference current for the CPUCLK pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the
appropriate current.
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
"Complementory" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current outputs and
external resistors are required for voltage bias.
3.3V LVTTL input for selecting the current multiplier for CPU outputs.
3.3V, 14.318MHz reference clock output.
0466B—03/17/04
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