ICS87949-01 Datasheet, PDF (7/13 Pages) Integrated Circuit Systems – LOW SKEW ÷1, ÷2 CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS87949-01
LOW SKEW ÷1, ÷2
CLOCK GENERATOR
TABLE
4F.
LVPECL
DC
CHARACTERISTICS,
V_DD
=
3.3V±5%,
V
DDX
=
2.5V±5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
PCLK
I_IH
Input High Current
nPCLK
V_DD = V_IN = 3.465V
V_DD = V_IN = 3.465V
150
5
PCLK
I_IL
Input Low Current
nPCLK
V_DD = 3.465V, V_IN = 0V
V_DD = 3.465V, V_IN = 0V
-5
-150
V_PP
Peak-to-Peak Input Voltage
0.3
1
V_CMR
Common Mode Input Voltage; NOTE 1, 2
GND + 1.5
V_DD
NOTE 1: Common mode voltage is defined as V .
IH
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is V_DD + 0.3V.
Units
µA
µA
µA
µA
V
V
TABLE
5B.
AC
CHARACTERISTICS,
V_DD
=
3.3V±5%,
V
DDX
=
2.5V±5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
tp_LH
tp_HL
tsk(b)
tsk(o)
tsk(w)
tsk(pp)
t_R
t_F
odc
Input Frequency
Propagation Delay,
Low to High; NOTE 1
Propagation Delay,
High to Low; NOTE 1
Bank Skew; NOTE 2, 7
Output Skew; NOTE 3, 7
Multiple Frequency Skew;
NOTE 4, 7
Part-to-Part Skew; NOTE 5, 7
Output Rise Time; NOTE 6
Output Fall Time; NOTE 6
Output Duty Cycle
f ≤ 250MHz
f ≤ 250MHz
Measured on rising edge at V_DDx/2
Measured on rising edge at V_DDx/2
Measured on rising edge at V_DDx/2
Measured on rising edge at V_DDx/2
20% to 80%
20% to 80%
250
3.5
3.5
100
200
350
500
700
700
50
t_EN
Output Enable Time;NOTE 6
f = 10MHz
t_DIS
Output Disable Time;NOTE 6
f = 10MHz
All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the V_DD/2 of the input to V_DDx/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
Measured at V_DDx/2.
NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages
and equal load conditions.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDx/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ns
ps
ps
ps
ps
ps
ps
%
ns
ns
87949AY-01
www.icst.com/products/hiperclocks.html
7
REV. A JANUARY 2, 2002