ICS87949-01 Datasheet, PDF (1/13 Pages) Integrated Circuit Systems – LOW SKEW ÷1, ÷2 CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS87949-01
LOW SKEW ÷1, ÷2
CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87949-01 is a low skew, ÷1, ÷2 Clock
,&6
Generator and a member of the HiPerClockS™
HiPerClockS™ _{family of High Performance Clock Solutions from}
ICS. The ICS87949-01 has selectable single
ended clock or LVPECL clock inputs. The single
ended clock input accepts LVCMOS or LVTTL input levels.
The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL
input levels. The low impedance LVCMOS outputs are de-
signed to drive 50Ω series or parallel terminated transmis-
sion lines. The effective fanout can be increased from 15 to
30 by utilizing the ability of the outputs to drive two series
terminated lines.
The divide select inputs, DIV_SELx, control the output frequency
of each bank. The outputs can be utilized in the ÷1, ÷2 or a
combination of ÷1 and ÷2 modes. The master reset input, MR/
nOE, resets the internal frequency dividers and also controls
the active and high impedance states of all outputs.
The ICS87949-01 is characterized at 3.3V core/3.3V output and
3.3V core/ 2.5V output. Guaranteed bank, output and part-to-
part skew characteristics make the ICS87949-01 ideal for those
clock distribution applications demanding well defined perfor-
mance and repeatability.
FEATURES
• 15 single ended LVCMOS outputs, 7Ω typical output
impedance
• Selectable LVCMOS or LVPECL clock inputs
• CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum input frequency: 250MHz
• Output skew: 200ps (maximum)
• Part-to-part skew: 500ps (typical)
• Multiple frequency skew: 350ps (maximum)
• 3.3V input, outputs may be either 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Functionally compatible to the MPC949 in a smaller footprint
requiring less board space
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
CLK0 0
0
÷1
CLK1 1
÷2
1
PCLK
R
nPCLK
0
PCLK_SEL
1
DIV_SELA
0
1
DIV_SELB
0
1
DIV_SELC
0
1
DIV_SELD
MR/nOE
QA0 - QA1
QB0 - QB2
QC0 - QC3
MR/nOE
CLK_SEL
VDD
CLK0
CLK1
PCLK
nPCLK
PCLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
ICS87949-01
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
nc
GND
QC0
VDDC
QC1
GND
QC2
VDDC
QC3
GND
GND
QD5
QD0 - QD5
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87949AY-01
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 2, 2002