ICS87949-01 Datasheet, PDF (2/13 Pages) Integrated Circuit Systems – LOW SKEW ÷1, ÷2 CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS87949-01
LOW SKEW ÷1, ÷2
CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
1
2
Name
MR/nOE
CLK_SEL
Type
Input Pulldown
Input Pulldown
Description
Master reset and output enable. Resets outputs to tristate.
Enables and disables all outputs. LVCMOS interface levels.
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
3
V_DD
Power
Positive supply pin. Connect to 3.3V.
4, 5
CLK0, CLK1 Input Pullup LVCMOS / LVTTL clock inputs.
6
PCLK
Input Pulldown Non-inverting differential LVPECL clock input.
7
nPCLK
Input Pullup Inverting differential LVPECL clock input.
8
PCLK_SEL
9
DIV_SELA
10
DIV_SELB
11
DIV_SELC
12
13, 14, 18,
22, 26, 27,
31, 35, 39,
43, 44, 48
15, 17,
19, 21,
23, 25
DIV_SELD
GND
QD0, QD1,
QD2, QD3,
QD4, QD5
Input
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
PCLK select input.
Controls frequency division for Bank A outputs.
LVCMOS interface levels.
Controls frequency division for Bank B outputs.
LVCMOS interface levels.
Controls frequency division for Bank C outputs.
LVCMOS interface levels.
Controls frequency division for Bank D outputs.
LVCMOS interface levels.
Power
Power supply ground. Connect to ground.
Output
Bank D outputs. LVCMOS interface levels.
7Ω typical output impedance.
16, 20, 24,
28, 30,
32, 34
29, 33
36
V_DDD
QC3, QC2,
QC1, QC0
V_DDC
nc
Power
Output
Power
Unused
Positive supply pins for Bank D outputs. Connect to 3.3V or 2.5V.
Bank C outputs. LVCMOS interface levels.
7Ω typical output impedance.
Positive supply pins for Bank C outputs. Connect to 3.3V or 2.5V.
No connect.
37, 41
38, 40,
42
45, 47
V_DDB
QB2, QB1,
QB0
QA1, QA0
Power
Output
Output
Positive supply pins for Bank B outputs. Connect to 3.3V or 2.5V.
Bank B outputs. LVCMOS interface levels.
7Ω typical output impedance.
Bank A outputs. LVCMOS interface levels.
7Ω typical output impedance.
46
V_DDA
Power
Positive supply pins for Bank A outputs. Connect to 3.3V or 2.5V.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87949AY-01
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 2, 2002