ICS87949-01 Datasheet, PDF (4/13 Pages) Integrated Circuit Systems – LOW SKEW ÷1, ÷2 CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS87949-01
LOW SKEW ÷1, ÷2
CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V_DDx
Inputs, V_I
Outputs, V_O
Package Thermal Impedance, θ_JA
Storage Temperature, T
STG
4.6V
-0.5V to V_DD + 0.5V
-0.5V to V_DD + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_DD = V_DDX = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum
V_DD
Positive Supply Voltage
*V_DDx
Output Supply Voltage
I_DD
Core Supply Current
**I
DDx
Output Supply Current
*V_DDx denotes V_DDA, V_DDB, V_DDC, V_DDD.
**I_DDx denotes I_DDA, I_DDB, I_DDC, I_DDD.
3.135
3.135
Typical
3.3
3.3
50
14
Maximum
3.465
3.465
Units
V
V
mA
mA
TABLE 4B. LVCMOS DC CHARACTERISTICS, V_DD = V_DDX = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
V_IH
Input
High Voltage
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
Test Conditions
Minimum Typical
2
CLK0, CLK1
2
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
V_IL
Input
Low Voltage
CLK_SEL, PCLK_SEL,
MR/nOE
-0.3
CLK0, CLK1
-0.3
DIV_SELA, DIV_SELB,
I_IH
Input
High Current
DIV_SELC, DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
*V_DDx = V_IN = 3.465V
CLK0, CLK1
*V_DDx = V_IN = 3.465V
DIV_SELA, DIV_SELB,
I_IL
Input
DIV_SELC, DIV_SELD,
CLK_SEL, PCLK_SEL,
*V_DDx = 3.465V, V_IN = 0V
-5
Low Current _MR/nOE
CLK0, CLK1
*V_DDx = 3.465V, V_IN = 0V
-150
V_OH
Output High Voltage; NOTE 1
2.6
V_OL
Output Low Voltage; NOTE 1
I_OZL
Output Tristate Current Low
I_OZH
Output Tristate Current High
NOTE 1: Outputs terminated with 50Ω to V_DDx/2. See page 8, Figure 1A, 3.3V Output Load Test Circuit.
*NOTE: V_DDx denotes V_DD, V_DDA, V_DDB, V_DDC, V_DDD.
87949AY-01
www.icst.com/products/hiperclocks.html
Maximum Units
V + 0.3 V
DD
V_DD + 0.3
V
0.8
V
1.3
V
150
µA
5
µA
µA
µA
V
0.5
V
TBD
V
TBD
V
REV. A JANUARY 2, 2002
4