ICS85454-01 Datasheet, PDF (7/15 Pages) Integrated Circuit Systems – DIFFERENTIAL-TO-LVDS MULTIPLEXER

Integrated
Circuit
Systems, Inc.
ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V_DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The
ratio of R1 and R2 might need to be adjusted to position the
V_REF in the center of the input voltage swing.
VDD
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
IN
nIN
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
IN/nIN INPUT:
For applications not requiring the use of the differential input,
both IN and nIN can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from IN to
ground.
LVDS
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
85454AK-01
www.icst.com/products/hiperclocks.html
7
REV. B JUNE 16, 2006