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ICS8430-51 Datasheet, PDF (7/16 Pages) Integrated Circuit Systems – 600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8430-51
600MHZ, LOW JITTER
LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum Typical
VOH
Output High Voltage; NOTE 1
VCC - 1.4
V
Output Low Voltage; NOTE 1
OL
V - 2.0
CC
VSWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. See "Parameter Information" section,
"3.3V Output Load Test Circuit" figure.
Maximum
VCC - 1.0
V - 1.7
CC
1.0
Units
V
V
V
TABLE
5.
INPUT
FREQUENCY
CHARACTERISTICS,
V
CC
=
V
CCA
=
V
CCO
=
3.3V±5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
TEST_CLK; NOTE 1
14
25
MHz
fIN
Input Frequency XTAL1, XTAL2; NOTE 1
S_CLOCK
14
25
MHz
TBD
MHz
NOTE 1: For the input crystal and reference frequency range, the M value must be set for the VCO to operate within the
200MHz to 700MHz range. Using the minimum input frequency of 14MHz, valid values of M are 115 ≤ M ≤ 400.
Using the maximum frequency of 25MHz, valid values of M are 64 ≤ M ≤ 224.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum Typical Maximum
Fundamental
14
25
50
70
7
Units
MHz
Ω
pF
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
FMAX
tjit(cc)
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1, 3
600
MHz
17
ps
tjit(per) Period Jitter, RMS; NOTE 1
2.6
ps
tsk(o) Output Skew; NOTE 2, 3
50
ps
tR
Output Rise Time
tF
Output Fall Time
M, N to nP_LOAD
200
700
ps
200
700
ps
5
ns
tS
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
ns
5
ns
M, N to nP_LOAD
5
ns
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
ns
5
ns
odc
Output Duty Cycle
47
53
%
tLOCK
PLL Lock Time
1
ms
Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
7