ICS8430-51 Datasheet, PDF (10/16 Pages) Integrated Circuit Systems – 600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8430-51
600MHZ, LOW JITTER
LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 5A and 5B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
F_OUT
Z_o = 50Ω
Z_o = 50Ω
F_IN
Z
o
=
50Ω
50Ω
1
RTT =
Z_o
(V + V / V –2) –2
OH
OL CC
Z_o = 50Ω
50Ω
RTT
V - 2V
CC
F_OUT
5
2 ^Zo
Z_o = 50Ω
3.3V
5
2 ^Zo
Z_o = 50Ω
F
IN
Z_o = 50Ω
3
2 ^Zo
Z
o
=
50Ω
3
2 ^Zo
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
LAYOUT GUIDELINE
The schematic of the ICS8430-51 layout example used in
this layout guideline is shown in Figure 6A. The ICS8430-51
recommended PCB board layout for this example is shown
in Figure 6B. This layout example is used as a general guide-
line. The layout in the actual system will depend on the
selected component types, the density of the components,
the density of the traces, and the stack up of the P.C. board.
U1
1
2
3
4
M5
M6
M7
5 ^M8
6
7
8
N0
N1
N2
GND
8430-01
C14
0.1u
X1
24
XTAL1
REF_IN
nXTAL_SEL
23
22
21
VCCA ₂₀
S_LOAD
S_DATA
S_CLOCK
19
18
17
MR
REF_IN
XTAL_SEL
S_LOAD
S_DATA
S_CLOCK
MR
C11
0.01u
R7
10
C16
22u
Termination A
VDD
C15
0.1u
R1
R3
125
125
Zo = 50 Ohm
IN+
TL1
Zo = 50 Ohm
IN-
TL2
R2
R4
84
84
VDD
Termination
B (Not shown
in the layout)
IN+
IN-
R2
R1
50
50
R3
50
8430AY-51
FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT
www.icst.com/products/hiperclocks.html
10
REV. D FEBRUARY 11, 2003