ICS8430-51 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – 600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8430-51
600MHZ, LOW JITTER
LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8430-51 features a fully integrated PLL and therefore requires no external components for setting the loop band-
width. A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector. With a 16MHz crystal, this provides a 1MHz reference frequency. The VCO of the
PLL operates over a range of 200MHz to 700MHz. The output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8430-51 support two input modes, programmable M divider and N output divider.
The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode,
the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 through N2 is passed directly to the M divider
and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be
hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up.
The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal
frequency and the M divider is defined as follows:
fVCO
=
fxtal
16
x
2M
The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock for a 16MHz reference are defined as 100 ≤ M ≤ 350. The frequency out is
defined as follows:
fout
=
fVCO
N
=
fxtal
16
x
2M
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider
when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output
divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0.
The internal registers T0 and T1 determine the state of the TEST output as follows:
T1 T0
00
01
10
11
TEST Output
LOW
S_Data
Output of M divider
CMOS Fout
S_CLOCK
SERIAL LOADING
S_DATA
S_LOAD
T1 T0 N2 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0
tt
SH
nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N2
M, N
nP_LOAD
tt
SH
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
8430AY-51
www.icst.com/products/hiperclocks.html
2
REV. D FEBRUARY 11, 2003