ICS673-01 Datasheet, PDF (7/9 Pages) Integrated Circuit Systems – PLL Building Block

ICS673-01
PLL Building Block
Avoiding PLL Lockup
In some applications, the ICS673 can “lock up” at
the maximum VCO frequency. This is usually
caused by power supply glitches or a very slow
power supply ramp. This situation also occurs if
the external divider starts to fail at high input
frequencies. The usual failure mode of a divider
circuit is that the output of the divider begins to
miss clock edges. The phase detector interprets
this as a too low output frequency and increases
the VCO frequency. The feedback divider begins
to miss even more clock edges, and the VCO
frequency is continually increased until it is
running at the maximum. Whether caused by
power supply issues or by the external divider, the
loop can only recover by powering down the
circuit, asserting PD, or shorting the loop filter to
ground.
The simplest way to avoid this problem is to use
an external divider that always operates correctly
regardless of the VCO speed. Figures 2 and 3
show that the VCO is capable of high speeds. By
using the internal divide-by-four and/or the
CLK2 output, the maximum VCO frequency can
be divided by 2, 4, or 8 and a slower counter can
be used. Using the ICS673 internal dividers in
this manner does reduce the number of
frequencies that can be exactly synthesized by
forcing the total VCO divide to change in
increments of 2, 4, or 8.
If this lockup problem occurs, there are several
solutions, three of which are described below.
1.If the system has a reset or power good signal,
this should be applied to the PD pin, forcing
the ICS673 to stay powered down until the
power supply voltage has stabilized.
2.If no power good signal is available, a simple
power-on reset circuit can be attached to the
PD pin, as shown in Figure 4 below. When the
power supply ramps up, this circuit holds PD
asserted (device powered down) until the
capacitor charges up.
VDD
ICS673-01
R1
PD
C3
A. Basic Circuit
VDD
ICS673-01
R1
D1
PD
C3
B. Faster Discharge
Figure 4. Power-on Reset Circuits.
The circuit of Figure 4A is adequate in most
cases, but the discharge rate of capacitor C3
when VDD goes low is limited by R1. As this
discharge rate determines the minimum reset
time, the circuit of Figure 4B may be used when
a faster reset time is desired. The values of R1
and C3 should be selected to ensure that PD
stays below 1.0 V until the power supply is
stable.
3.A comparator circuit may be used to monitor
the loop filter voltage, as shown in Figure 5.
This circuit will dump the charge off the loop
filter by asserting PD if the VCO begins to run
too fast, and the PLL can recover. A good
choice for this comparator is the National
Semiconductor LMC7211BIM5X. It is low
MDS 673-01 D
7
Revision 022500
Printed 11/15/00
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